L-Systems and Koch Island Fractals

erik dawe

ed267

 

N = 4 , α = 22.50

ω: F

p:F—>FF-[-F+F+F]+[+F-F-F]

 

Introduction

 

The goal of this lab was to explore the creation of L-systems on a field programmable gate array (FPGA). An L-system, short for Lindenmayer system, is a theoretical framework for studying the development of simple multicellular organisms [1]. Using basic principles of geometry, a graphical interpretation of L-systems is possible that can be used to render fractals and life-like visualizations of plant structures that show the basic growth and development process of plants. Such modeling efforts can be useful as they offer a litmus test for scientists interested in understanding how well they actually understand the biology of the organisms under investigation.

L-system are created by a process called rewriting, which is a serial process of creating complex objects by successively supplanting parts of a simple initial object into a set of rewriting rules (known as productions in the parlance of L-system) to create a more complex system. The processing capability of the FPGA, which is programmed using a hardware description language (HDL), is inherently parallel by nature. The strength and versatility of the FPGA lies in performing myriad operations at once. While they can be configured to perform operations and calculations in an explicitly serial fashion, accomplishing such functionality is more circuitous than with other devices such as microcontrollers, which are typically programmed in a serial language such as C. This is because code written in Verilog actually creates new hardware that functions in parallel, not just instructions for pre-existing hardware. Thus the recursive, serial nature of L-systems makes modeling them on an FPGA a non-trivial exercise.  The advantage of using FPGAs is that the celerity and volume of calculations is greatly enhanced due to the application specific nature of the hardware, and the parallelism in calculation that occurs when allowed. This yields significant advantages for highly iterative, calculation intensive models that take significant calculation time for a serial processor, but happen almost instantly with an FPGA as a result of the specific parallelized structure of the design.

 

 

N = 5 , α = 90

ω: F-F-F-F

p:F—>FF-F-F-F-F-F+F

 

Rationale

 

In recent years I have become increasingly interested in techniques for modeling living organisms through artificial means such as circuits and networks. Having been introduced to L-systems by professor Bruce Land, I found the juxtaposition of simplicity and ability to accurately describe plant growth seen so readily in nature fascinating. I thought the 576 final project was a unique opportunity to explore my interest in L-systems and further learn how to use the FPGA to solve another unusual problem.

 

The Designs

 

The L-systems I chose to create were found in the book The Algorithmic Beauty of Plants, by Aristid Lindenmayer(the L-system namesake) and Prezemyslaw Prusinkiewicz, and are present throughout this page.

 

Logical Structure

 

The design intent of the project was to explore the creation of an L-system by writing Verilog code for an FPGA. Each L-system would have three basic components: the generating principal/instruction set for the L-system comprised of an axiom and concomitant productions; the Verilog code used to build the L-system on the FPGA; and the resulting image of the L-system to be displayed on a VGA monitor. I decided to begin with the most basic L-system definition, construct it in hardware on the FPGA, and continue to add as much complexity as the time allotted for the final project would allow. My goal was to created an N=4 L-system with the ability to branch and be stochastic. The design paradigm was as follows : Each L-system axiom would be designed with its correctness verified by graphical display on a VGA monitor. The subsequent productions would be added and verified visually like the axiom. The L-system would then be recursively iterated with each iteration verified graphically along the way. As I aimed to increase L-system definition versatility, I would also work towards building L-systems of greater iterations. Creating L-systems of higher iterations was of cardinal interest for it is the area where an FPGA can offer the greatest returns with respect to speeding up computation time.

 

 

N = 4 , α = 90

ω: F-F-F-F

p:F—>F-F+F+FF-F-F+F

 

The Definition Of An L-system

 

Let there exist an alphabet V, which is a collection of all elements that can exist as variables. Let V* be the set of all words over V, and let V+ be the set of all non-empty words over V. Let there also exist ω which shall be call the axiom, which is a continuous, non-empty string of elements of the set V, which shall define the initial state of the system. Lastly, let there exist P, which shall be defined as a set of productions, i.e. rules, which shall describe the manner in which all variables (which are a subset of V) can be placed and combined with other variables.  Let each production P  be composed of two string p1—>p2 where p1 is known as the predecessor and p2 is known and the successor. These three elements delineate the L-system G which is define by the following mathematical tuple

 

G = {V, ω, P},

 

In general, L-system are deterministic if the relationship between the predecessor and successor is monotonic such that each p1—>p2 is unique. To illustrate this somewhat abstract concept in action, allow for the example of a simple N=1 multi-production L-system used to describe the growth of bacteria Anabaena catenula, borrowed from Lindenmayer and Prusinkiewicz[1].

The L-system,

ω: ar

p1:ar—>albr

p2: al—>blar

p3:br—>ar

p4:bl—>al

 

The following sequence was generated from the above L-system and can be verified upon simple inspection.

ar

albr

blarar

alalbralbr

blarblararblarar

 

Geometric Interpretation

 

To actually generate geometrical interpretations of L-system strings in an intelligent way to create fractals and plant-like structures, the LOGO programming language turtle-graphics approach was used.

LOGO is a programming language that is used primarily for functional programming. It is best known for its turtle-graphics method of displaying vectors using a cursor, (aka turtle), that walks about a standard 2-D Cartesian plane. The state of the turtle is define as triplet (x,y,α) where (x,y) represents the turtleŐs location on the 2-D Cartesian plane, and α is an angle that represents the direction the turtle is facing. By changing position (x,y) and incrementing or decrementing the angle α, we can instruct the turtle around a 2-D Cartesian plane. By having it paint or not paint locations (in our case pixels on our VGA monitor) that it walks over we can follow the rules of our L-system and paint out our fractal or plant.

The following are the basic commands and explanations used to generate all L-system designs for this project.

 

F    —>    Move the turtle forward one step of length l in the direction that it is currently facing and draw a line segment from its previous location to its new, current location

 

f    —>    Move the turtle forward one step of length l in the direction that it is currently facing without drawing a line segment

 

+    —>     Increment turtle direction left by one angular unit (e.g. 900, 450, 22.50, etc)

 

-  —>     Increment turtle direction right by one angular unit (e.g. 900, 450, 22.50, etc)

 

[   —>    Push the current state of the turtle (x,y,α) in a stack for storage

 

]   —>    Pop a state of the turtle (x,y,α) from the stack and make it the current state

 

                                                                                                                        Figure 1.

 

Figure 1. shows the movement of a turtle that begins at START facing North and arrives at FINISH by following instructions below.

FF-FF-FF+F

 

N = 3 , α = 22.50

Stochastic(above three pictures generated from same exact code)

ω: F

p1:F—>F[ +F+F]+[+F-F-F] (P=.33)

p2:F—>F[ +F+F]+[-F] (P=.33)

p2:F—>F[-F+F+F]+[+F-F-F] (P=.34)

 

 

Design Considerations

 

The design paradigm chosen to achieve the serialized recursive execution of the L-system was the largest design decision, and boiled down to two options: I could either build a processor that would execute an L-system—this would be more compact and perhaps more elegant solution; or I could essentially build a collection of nested, communicating state machines. As I wanted to build several different L-systems—starting simple and then begin adding complexity piece meal—and have the capability to evolve, update, and change my L-system definition using different axioms and productions, I opted to go with the nested state machines approach as it seemed a more tractable approach for debugging and making modifications. What ultimately made this decision was that my early work and thought into developing a processor began to engender many specific structures and functionality unique to each L-system that did not seem plastic, easily adaptable or transferable to other L-system axioms and productions.

 

N = 4 , α = 900

ω: F-F-F-F

p:FF-F+F-F-FF

 

Hardware Design

All hardware for this class was limited to the FPGA and was written in the HDL Verilog. All of the plants and fractals generated for this project share a similar core design of multiple, nested state machine processors. The top level state machine is responsible for executing the axiom, ω. The axiom then calls the subsequent productions, which are also state machines. Each state of the state machine executes either a production or a sub-production (a production within a production). In the case for an N=1 design, each step of the axiom leads to the execution of a production which leads directly to a drawing of the turtle. In the case for an N=2 design, each step of the axiom leads to a step in the production, which leads to a step in a sub production. Here, each sub-production (which in this case is the lowest level production) is executed in full. This corresponds to each lowest level production updating the position of the turtle and writing it to the VGA monitor. Once a sub-production is executed, control is then sent back up to the next top-level production where the next step of the higher level production is executed. This continues until the axiom is reached for further top-level instruction. One can imagine for higher N the process is the same, with each production incrementing, and then cascading down, incrementing the next sub production, until the lowest level writing production is reached.

Naturally, as each production is reached on the way down, the state of the turtle is altered. In going through the steps of a production which is executed by means of a state machine, the state machine state variable is incremented after each step of the production. This way, when a higher level state machine is returned to from a lower level or nested state machine, its state variable has been incremented so that the state machine goes to the next step of the production-state of the state machine. This occurs when a sub-production is finished and returns control to the next higher production. The main control logic for the entire L-system is contained in the lowest level production in the form of a master IF ELSE conditional statement that has 2n IF ELSE conditionals. Each one of these conditionals is responsible for clearing registers and redirecting the L-system calculation flow onwards.

 

N = 4 , α = 900

ω: F-F-F-F

p:FF-F--F-F

 

Although there are many different stages and states directing the turtle in a complex combination directions, there is only one current writing position of the turtle to keeping track of at a time. In the case of the Koch Island fractals, the angle increment was 900. To keep track of the turtle direction a 2 bit, four combination turtle direction register was created.

{(0,0) ,  (0,1) , (1,0) ,  (1,1)}  = {0,1,2,3}

Each unique 2 bit combination mapped to one of 4 possible directions that was a multiple of 900. Every time a + or – was encounter in the execution of the axiom or production, the turtle_direction register was incremented or decremented accordingly. In the instance that a turtle turned around more than 3600, the register simply wrapped around to the beginning and preserved the proper direction as intended by the L-system.  This is illustrated below in figure 2.

 Figure 2.

The same scheme was used for the plants that were generated, which used a 22.50 angle. Luckily, the angle used for our plants, 22.50 divides into 360 sixteen times, thus a 4 bit turtle direction vector with sixteen unique bit patterns was created and used the exact same way.

As the angle increment for the Koch Island is 900, the turtle only needs to move in straight lines. Thus, just before the write stage where one pixel is written, the x_position or y_position registers are updated by one for each pixel a step l pixels long. In other words, for an 8 pixel step l, it is updated 8 times for a given turtle_direction. This is accomplished by entering a state in the lowest level production which assigns a one pixel increment, in either the x or y position as specified, based upon the value of the turtle_direction register. This is easily kept track of by having the state variable for this sub-state machine be the value of the turtle_direction register.  After the address is update by one, the lowest level moves to the write stage, writes the new location, and updates a counter which counts l times for the update length l. Once all the pixels of a given length for a specified direction are drawn, the incrementing-writing loop that writes a step of l pixels in length is exited and the next stage of the production is entered.

N = 4 , α = 900

ω: F-F-F-F

p:FF-F-F-F-FF

 

The exact same thing is done for the 22.50 angle that is used in the plants, except that to execute a line segment of a given length for a given angle, both the x_position and y_position registers must be updated. As we wanted to minimize the number of pixels to create each 22.50 angle length so to engender the largest N-size plant to fit on the screen, the smallest number of pixels that could resolve a 22.50 angle was used. This turned out to be four pixels. Thus, for a given turtle_direction register value corresponding to a particular angle that is a multiple 22.50 , a unique line could be drawn. These lines are illustrated below in Figure 3.

 

                                                                                                            Figure 3.

Each one of the lines is composed of four pixels and was hard coded in the state machine that used the turtle_direction register as its state variable. This state machine was visited four times, once for drawing each pixel of the four pixel angled line.  This four pixel line count was maintained by a register which reset after four pixels, i.e. a complete angled line length, had been drawn.

To achieve branching, registers were created which stored and retrieved the turtle triplet values (x,y,α)  at different points as specified in the L-system. All productions and sub-productions had their own unique registers so that multiple positions for different production levels could be saved at the same time to create compound branching structures.

I was also able to create a stochastic L-system that grew multiple trees, all of which grew differently. Stochastic L-systems work by having multiple productions for each production stage, each with a probability of being chosen as the production to be executed for that production. Each of the multiple productions are given an equal probability of being chosen, but only one production is actually chosen and used for each stage. Thus each time each production is enter a different production is chosen. Creating this functionality was accomplished in hardware by creating a linear feedback shift register to generate random numbers. Three random bits of the linear feedback shift register output were concatenated to make a random 3 bit number. Each production stage had three different probability productions created by a conditional IF statement that said if the random number was either X or Y or Z, execute the statement/production below. Thus, if the random 3 bit number matched one of the numbers assigned to the conditional statement for the production, that production was executed.  Multiple stochastic trees where created on the same screen by simply rerunning the L-system once it was finish with different X coordinate values.

For the early designs, increments lengths of sixteen 320x240 resolution pixels where used to define one forward length l. However, as the N value increased, the size of the resultant image displayed on the VGA monitor became too large to be displayed. This demanded a decrease in increment length l by a factor of 2 for each N value increase. In the N=4 and N=5 case the resultant image required a reduction of pixel length down to four pixels, and an increase of the screen resolution to 640x480.  Actually, N=5 never fit on the screen and all that showed was what was produced by N =4 (which barely fit at 640x480!). Increasing the resolution proved to be slightly tricky due to a slightly obscure pixel addressing scheme, and a non-intuitive one-cycle delay between the code executing the L-system and the VGA controller; both of which will be expounded upon below.

There are two main parts to writing pixels on the screen: the location, or address of the screen that is being written to (which is limited to 18 bits), and the actual color/data which is being written(which is limited to 16 bits). The address of the pixel being written is placed in the register addr_reg which is loaded into the SRAM address register SRAM_ADDR, both of which are 18 bit registers. For a 320x240 resolution this is fine and the x_position and y_position registers (both 9 bits) can be concatenated into the 18 bit register addr_reg. The color/data being written to the pixel is put in a 16 bit data register called data_reg, which is loaded into SRAM_DQ. For a 320x240 resolution, this typically allows for 4 bits of red, 4 bits of green, 4 bits of blue, and 4 bits left undefined . The critical knowledge to increasingly the resolution from 320x240 to 640x480  is accurately understanding the mapping relationship between a 320x240 and 640x480 pixel— which is that four pixels of 640x480 resolution are used to create one pixel at 320x240 resolution as shown below in figure number 4.

 

Figure 4.

 

Thus, the 4 bits of red, 4 bits of green, 4 bits of blue in an SRAM_DQ assignment for one 320x240 pixel are actually color assignments in the SRAM_DQ for four pixels at 640x480 resolution. This relationship is further illustrated below in figure 5.

 

                                                                                                            Figure 5.

 

Thus, if you want to go from 320x240 to 640x480, as you increase your ability to resolve pixels by a factor of two, you reduce your ability to resolve color depth from 16 bits per pixel to 4 bits per pixel as each 640x480 pixel only has 4 bits of color available since we are limited to a 16 bit register.

Now, for addressing a pixel on a 640x480 resolution, the size of the x and y address registers, x_position and y_position, must increase to 10 bits, with the top 9 bits [9:1] of x_position and y_position being concatenated and sent to SRAM_ADDR, which must remain 18 bits due to memory limitations. This provides the coarse grain location. To chose between one of the 4 fine grained, 640x480 pixel locations, the last bits x_position[0] and y_position[0] are inspected to resolve one of 4 possible locations. Each of these locations are then assigned a 4 bit color depth (R,G,G,B) in the SRAM_DQ register with a conditional assign statement to the VGA red, green, and blue channels based on the decoded bits (x_position[0], y_position[0]). The decoding of single 320x240 pixel to a 640x480 pixel via x_position[0] and y_position[0] is shown below in figure 6.

 

                                                                                                            Figure 6.

The last additional complication arises because the VGA RGB assignment is combinatorial as can be seen below and doesnŐt sync with the data sent to VGA controller (it arrives a cycle early).

assign  mVGA_R =

{(xi_hold_reg == 2'b00 ? SRAM_DQ[15] :

 xi_hold_reg == 2'b01 ? SRAM_DQ[11] :

 xi_hold_reg == 2'b10 ? SRAM_DQ[7] :

 xi_hold_reg == 2'b11 ? SRAM_DQ[3] :

 1'b0), 9'b0};

 

assign  mVGA_G =

{(xi_hold_reg == 2'b00 ? SRAM_DQ[14:13] :

 xi_hold_reg == 2'b01 ? SRAM_DQ[10:9] :

 xi_hold_reg == 2'b10 ? SRAM_DQ[6:5] :

 xi_hold_reg == 2'b11 ? SRAM_DQ[2:1] :

 2'b0), 8'b0} ;

 

assign  mVGA_B =

{(xi_hold_reg == 2'b00 ? SRAM_DQ[12] :

 xi_hold_reg == 2'b01 ? SRAM_DQ[8] :

 xi_hold_reg == 2'b10 ? SRAM_DQ[4] :

 xi_hold_reg == 2'b11 ? SRAM_DQ[0] :

 1'b0), 9'b0} ;

 

Thus for the VGA to be synchronized to the writing logic, the information sent to the combinatorial RGB assign statements must be delayed one cycle. This is done by storing it to a register which is loaded on the same clock as the rest of the processor.

 

Results

I was able to achieve all of the functionality I had set out to achieve for this project. I was able to successfully create various N= 4 Koch Islands, a N=4 branching plant, and a set of stochastic trees.

 

Appendix: Acknowledgements, References, Source Code

 

I would like to thank instructor Bruce Land and TA Xi for their patience and support throughout the semester. As I worked alone on all of the group projects, I would like to thank all of the students in the class who helped me out when I got stuck and served as my temporary/de facto partners now and then. I would like to thank Steve for turning me on to how cool plants are, Deborah for putting up with me while I took this class, and most of all my mom and dad, Jean and Barry, and my grandparents, Rina and Bill, for inspiring me and giving me the confidence that I can do anything I put my mind to despite being an idiot.

 

 

 

for my Dad.

 

 

References

 

[1] Prusinkiewcz & Lindenmayer; The Algorithmic Beauty of Plants, 1997

 

 

 

Source Code (For N=4 plant at top of page)

 

 

 

module DE2_Default

            (

                        ////////////////////    Clock Input                  ////////////////////   

                        CLOCK_27,                                                                  //          27 MHz

                        CLOCK_50,                                                                  //          50 MHz

                        EXT_CLOCK,                                                              //          External Clock

                        ////////////////////    Push Button                  ////////////////////

                        KEY,                                                                            //          Pushbutton[3:0]

                        ////////////////////    DPDT Switch                ////////////////////

                        SW,                                                                                          //          Toggle Switch[17:0]

                        ////////////////////    7-SEG Dispaly  ////////////////////

                        HEX0,                                                                          //          Seven Segment Digit 0

                        HEX1,                                                                          //          Seven Segment Digit 1

                        HEX2,                                                                          //          Seven Segment Digit 2

                        HEX3,                                                                          //          Seven Segment Digit 3

                        HEX4,                                                                          //          Seven Segment Digit 4

                        HEX5,                                                                          //          Seven Segment Digit 5

                        HEX6,                                                                          //          Seven Segment Digit 6

                        HEX7,                                                                          //          Seven Segment Digit 7

                        ////////////////////////            LED                 ////////////////////////

                        LEDG,                                                                         //          LED Green[8:0]

                        LEDR,                                                                          //          LED Red[17:0]

                        ////////////////////////            UART   ////////////////////////

                        UART_TXD,                                                                 //          UART Transmitter

                        UART_RXD,                                                                 //          UART Receiver

                        ////////////////////////            IRDA    ////////////////////////

                        IRDA_TXD,                                                                  //          IRDA Transmitter

                        IRDA_RXD,                                                                  //          IRDA Receiver

                        /////////////////////   SDRAM Interface                      ////////////////

                        DRAM_DQ,                                                                  //          SDRAM Data bus 16 Bits

                        DRAM_ADDR,                                                              //          SDRAM Address bus 12 Bits

                        DRAM_LDQM,                                                             //          SDRAM Low-byte Data Mask

                        DRAM_UDQM,                                                             //          SDRAM High-byte Data Mask

                        DRAM_WE_N,                                                              //          SDRAM Write Enable

                        DRAM_CAS_N,                                                             //          SDRAM Column Address Strobe

                        DRAM_RAS_N,                                                             //          SDRAM Row Address Strobe

                        DRAM_CS_N,                                                               //          SDRAM Chip Select

                        DRAM_BA_0,                                                               //          SDRAM Bank Address 0

                        DRAM_BA_1,                                                               //          SDRAM Bank Address 0

                        DRAM_CLK,                                                                //          SDRAM Clock

                        DRAM_CKE,                                                                //          SDRAM Clock Enable

                        ////////////////////    Flash Interface              ////////////////

                        FL_DQ,                                                                                    //          FLASH Data bus 8 Bits

                        FL_ADDR,                                                                    //          FLASH Address bus 22 Bits

                        FL_WE_N,                                                                   //          FLASH Write Enable

                        FL_RST_N,                                                                  //          FLASH Reset

                        FL_OE_N,                                                                    //          FLASH Output Enable

                        FL_CE_N,                                                                    //          FLASH Chip Enable

                        ////////////////////    SRAM Interface             ////////////////

                        SRAM_DQ,                                                                  //          SRAM Data bus 16 Bits

                        SRAM_ADDR,                                                              //          SRAM Address bus 18 Bits

                        SRAM_UB_N,                                                               //          SRAM High-byte Data Mask

                        SRAM_LB_N,                                                               //          SRAM Low-byte Data Mask

                        SRAM_WE_N,                                                              //          SRAM Write Enable

                        SRAM_CE_N,                                                               //          SRAM Chip Enable

                        SRAM_OE_N,                                                               //          SRAM Output Enable

                        ////////////////////    ISP1362 Interface          ////////////////

                        OTG_DATA,                                                                //          ISP1362 Data bus 16 Bits

                        OTG_ADDR,                                                                //          ISP1362 Address 2 Bits

                        OTG_CS_N,                                                                 //          ISP1362 Chip Select

                        OTG_RD_N,                                                                 //          ISP1362 Write

                        OTG_WR_N,                                                                //          ISP1362 Read

                        OTG_RST_N,                                                               //          ISP1362 Reset

                        OTG_FSPEED,                                                             //          USB Full Speed,            0 = Enable, Z = Disable

                        OTG_LSPEED,                                                                        //          USB Low Speed,           0 = Enable, Z = Disable

                        OTG_INT0,                                                                  //          ISP1362 Interrupt 0

                        OTG_INT1,                                                                  //          ISP1362 Interrupt 1

                        OTG_DREQ0,                                                              //          ISP1362 DMA Request 0

                        OTG_DREQ1,                                                              //          ISP1362 DMA Request 1

                        OTG_DACK0_N,                                                          //          ISP1362 DMA Acknowledge 0

                        OTG_DACK1_N,                                                          //          ISP1362 DMA Acknowledge 1

                        ////////////////////    LCD Module 16X2                     ////////////////

                        LCD_ON,                                                                                 //          LCD Power ON/OFF

                        LCD_BLON,                                                                 //          LCD Back Light ON/OFF

                        LCD_RW,                                                                                 //          LCD Read/Write Select, 0 = Write, 1 = Read

                        LCD_EN,                                                                                  //          LCD Enable

                        LCD_RS,                                                                                  //          LCD Command/Data Select, 0 = Command, 1 = Data

                        LCD_DATA,                                                                 //          LCD Data bus 8 bits

                        ////////////////////    SD_Card Interface         ////////////////

                        SD_DAT,                                                                                  //          SD Card Data

                        SD_DAT3,                                                                    //          SD Card Data 3

                        SD_CMD,                                                                                 //          SD Card Command Signal

                        SD_CLK,                                                                                  //          SD Card Clock

                        ////////////////////    USB JTAG link ////////////////////

                        TDI,                                                                             // CPLD -> FPGA (data in)

                        TCK,                                                                            // CPLD -> FPGA (clk)

                        TCS,                                                                            // CPLD -> FPGA (CS)

                TDO,                                                                                    // FPGA -> CPLD (data out)

                        ////////////////////    I2C                   ////////////////////////////

                        I2C_SDAT,                                                                   //          I2C Data

                        I2C_SCLK,                                                                   //          I2C Clock

                        ////////////////////    PS2                  ////////////////////////////

                        PS2_DAT,                                                                     //          PS2 Data

                        PS2_CLK,                                                                    //          PS2 Clock

                        ////////////////////    VGA                 ////////////////////////////

                        VGA_CLK,                                                                   //          VGA Clock

                        VGA_HS,                                                                                 //          VGA H_SYNC

                        VGA_VS,                                                                                  //          VGA V_SYNC

                        VGA_BLANK,                                                              //          VGA BLANK

                        VGA_SYNC,                                                                 //          VGA SYNC

                        VGA_R,                                                                        //          VGA Red[9:0]

                        VGA_G,                                                                                  //          VGA Green[9:0]

                        VGA_B,                                                                        //          VGA Blue[9:0]

                        ////////////            Ethernet Interface          ////////////////////////

                        ENET_DATA,                                                               //          DM9000A DATA bus 16Bits

                        ENET_CMD,                                                                //          DM9000A Command/Data Select, 0 = Command, 1 = Data

                        ENET_CS_N,                                                                //          DM9000A Chip Select

                        ENET_WR_N,                                                              //          DM9000A Write

                        ENET_RD_N,                                                               //          DM9000A Read

                        ENET_RST_N,                                                             //          DM9000A Reset

                        ENET_INT,                                                                  //          DM9000A Interrupt

                        ENET_CLK,                                                                 //          DM9000A Clock 25 MHz

                        ////////////////        Audio CODEC              ////////////////////////

                        AUD_ADCLRCK,                                                          //          Audio CODEC ADC LR Clock

                        AUD_ADCDAT,                                                                        //          Audio CODEC ADC Data

                        AUD_DACLRCK,                                                          //          Audio CODEC DAC LR Clock

                        AUD_DACDAT,                                                                        //          Audio CODEC DAC Data

                        AUD_BCLK,                                                                 //          Audio CODEC Bit-Stream Clock

                        AUD_XCK,                                                                   //          Audio CODEC Chip Clock

                        ////////////////        TV Decoder                   ////////////////////////

                        TD_DATA,                                                       //          TV Decoder Data bus 8 bits

                        TD_HS,                                                                                    //          TV Decoder H_SYNC

                        TD_VS,                                                                                    //          TV Decoder V_SYNC

                        TD_RESET,                                                                 //          TV Decoder Reset

                        ////////////////////    GPIO   ////////////////////////////

                        GPIO_0,                                                                                   //          GPIO Connection 0

                        GPIO_1                                                                                    //          GPIO Connection 1

            );

 

////////////////////////            Clock Input                  ////////////////////////

input                            CLOCK_27;                                          //          27 MHz

input                            CLOCK_50;                                          //          50 MHz

input                            EXT_CLOCK;                                      //          External Clock

////////////////////////            Push Button                  ////////////////////////

input    [3:0]      KEY;                                                    //          Pushbutton[3:0]

////////////////////////            DPDT Switch                ////////////////////////

input    [17:0]    SW;                                                                  //          Toggle Switch[17:0]

////////////////////////            7-SEG Dispaly  ////////////////////////

output  [6:0]      HEX0;                                                  //          Seven Segment Digit 0

output  [6:0]      HEX1;                                                  //          Seven Segment Digit 1

output  [6:0]      HEX2;                                                  //          Seven Segment Digit 2

output  [6:0]      HEX3;                                                  //          Seven Segment Digit 3

output  [6:0]      HEX4;                                                  //          Seven Segment Digit 4

output  [6:0]      HEX5;                                                  //          Seven Segment Digit 5

output  [6:0]      HEX6;                                                  //          Seven Segment Digit 6

output  [6:0]      HEX7;                                                  //          Seven Segment Digit 7

////////////////////////////        LED                 ////////////////////////////

output  [8:0]      LEDG;                                                 //          LED Green[8:0]

output  [17:0]    LEDR;                                                  //          LED Red[17:0]

////////////////////////////        UART   ////////////////////////////

output                          UART_TXD;                                         //          UART Transmitter

input                            UART_RXD;                                         //          UART Receiver

////////////////////////////        IRDA    ////////////////////////////

output                          IRDA_TXD;                                          //          IRDA Transmitter

input                            IRDA_RXD;                                          //          IRDA Receiver

///////////////////////             SDRAM Interface          ////////////////////////

inout    [15:0]    DRAM_DQ;                                          //          SDRAM Data bus 16 Bits

output  [11:0]    DRAM_ADDR;                                      //          SDRAM Address bus 12 Bits

output                          DRAM_LDQM;                                     //          SDRAM Low-byte Data Mask

output                          DRAM_UDQM;                                     //          SDRAM High-byte Data Mask

output                          DRAM_WE_N;                                      //          SDRAM Write Enable

output                          DRAM_CAS_N;                                     //          SDRAM Column Address Strobe

output                          DRAM_RAS_N;                                     //          SDRAM Row Address Strobe

output                          DRAM_CS_N;                                       //          SDRAM Chip Select

output                          DRAM_BA_0;                                       //          SDRAM Bank Address 0

output                          DRAM_BA_1;                                       //          SDRAM Bank Address 0

output                          DRAM_CLK;                                        //          SDRAM Clock

output                          DRAM_CKE;                                        //          SDRAM Clock Enable

////////////////////////            Flash Interface  ////////////////////////

inout    [7:0]      FL_DQ;                                                            //          FLASH Data bus 8 Bits

output  [21:0]    FL_ADDR;                                            //          FLASH Address bus 22 Bits

output                          FL_WE_N;                                           //          FLASH Write Enable

output                          FL_RST_N;                                          //          FLASH Reset

output                          FL_OE_N;                                            //          FLASH Output Enable

output                          FL_CE_N;                                            //          FLASH Chip Enable

////////////////////////            SRAM Interface ////////////////////////

inout    [15:0]    SRAM_DQ;                                          //          SRAM Data bus 16 Bits

output  [17:0]    SRAM_ADDR;                                      //          SRAM Address bus 18 Bits

output                          SRAM_UB_N;                                       //          SRAM High-byte Data Mask

output                          SRAM_LB_N;                                       //          SRAM Low-byte Data Mask

output                          SRAM_WE_N;                                      //          SRAM Write Enable

output                          SRAM_CE_N;                                       //          SRAM Chip Enable

output                          SRAM_OE_N;                                       //          SRAM Output Enable

////////////////////    ISP1362 Interface          ////////////////////////

inout    [15:0]    OTG_DATA;                                        //          ISP1362 Data bus 16 Bits

output  [1:0]      OTG_ADDR;                                        //          ISP1362 Address 2 Bits

output                          OTG_CS_N;                                         //          ISP1362 Chip Select

output                          OTG_RD_N;                                         //          ISP1362 Write

output                          OTG_WR_N;                                        //          ISP1362 Read

output                          OTG_RST_N;                                       //          ISP1362 Reset

output                          OTG_FSPEED;                                     //          USB Full Speed,            0 = Enable, Z = Disable

output                          OTG_LSPEED;                                                //          USB Low Speed,           0 = Enable, Z = Disable

input                            OTG_INT0;                                          //          ISP1362 Interrupt 0

input                            OTG_INT1;                                          //          ISP1362 Interrupt 1

input                            OTG_DREQ0;                                      //          ISP1362 DMA Request 0

input                            OTG_DREQ1;                                      //          ISP1362 DMA Request 1

output                          OTG_DACK0_N;                                  //          ISP1362 DMA Acknowledge 0

output                          OTG_DACK1_N;                                  //          ISP1362 DMA Acknowledge 1

////////////////////    LCD Module 16X2         ////////////////////////////

inout    [7:0]      LCD_DATA;                                         //          LCD Data bus 8 bits

output                          LCD_ON;                                                         //          LCD Power ON/OFF

output                          LCD_BLON;                                         //          LCD Back Light ON/OFF

output                          LCD_RW;                                                         //          LCD Read/Write Select, 0 = Write, 1 = Read

output                          LCD_EN;                                                          //          LCD Enable

output                          LCD_RS;                                                          //          LCD Command/Data Select, 0 = Command, 1 = Data

////////////////////    SD Card Interface          ////////////////////////

inout                            SD_DAT;                                                          //          SD Card Data

inout                            SD_DAT3;                                            //          SD Card Data 3

inout                            SD_CMD;                                                         //          SD Card Command Signal

output                          SD_CLK;                                                          //          SD Card Clock

////////////////////////            I2C                   ////////////////////////////////

inout                            I2C_SDAT;                                           //          I2C Data

output                          I2C_SCLK;                                           //          I2C Clock

////////////////////////            PS2                  ////////////////////////////////

input                           PS2_DAT;                                             //          PS2 Data

input                            PS2_CLK;                                            //          PS2 Clock

////////////////////    USB JTAG link ////////////////////////////

input                            TDI;                                                     // CPLD -> FPGA (data in)

input                            TCK;                                                    // CPLD -> FPGA (clk)

input                            TCS;                                                    // CPLD -> FPGA (CS)

output                          TDO;                                                    // FPGA -> CPLD (data out)

////////////////////////            VGA                             ////////////////////////////

output                          VGA_CLK;                                           //          VGA Clock

output                          VGA_HS;                                                         //          VGA H_SYNC

output                          VGA_VS;                                                          //          VGA V_SYNC

output                          VGA_BLANK;                                      //          VGA BLANK

output                          VGA_SYNC;                                         //          VGA SYNC

output  [9:0]      VGA_R;                                                //          VGA Red[9:0]

output  [9:0]      VGA_G;                                                          //          VGA Green[9:0]

output  [9:0]      VGA_B;                                                //          VGA Blue[9:0]

////////////////        Ethernet Interface          ////////////////////////////

inout    [15:0]    ENET_DATA;                                       //          DM9000A DATA bus 16Bits

output                          ENET_CMD;                                        //          DM9000A Command/Data Select, 0 = Command, 1 = Data

output                          ENET_CS_N;                                        //          DM9000A Chip Select

output                          ENET_WR_N;                                      //          DM9000A Write

output                          ENET_RD_N;                                       //          DM9000A Read

output                          ENET_RST_N;                                     //          DM9000A Reset

input                            ENET_INT;                                          //          DM9000A Interrupt

output                          ENET_CLK;                                         //          DM9000A Clock 25 MHz

////////////////////    Audio CODEC              ////////////////////////////

output/*inout*/

            AUD_ADCLRCK;

                                    //          Audio CODEC ADC LR Clock

input                            AUD_ADCDAT;                                                //          Audio CODEC ADC Data

inout                            AUD_DACLRCK;                                  //          Audio CODEC DAC LR Clock

output                          AUD_DACDAT;                                                //          Audio CODEC DAC Data

inout                            AUD_BCLK;                                         //          Audio CODEC Bit-Stream Clock

output                          AUD_XCK;                                           //          Audio CODEC Chip Clock

////////////////////    TV Devoder                   ////////////////////////////

input    [7:0]      TD_DATA;                               //          TV Decoder Data bus 8 bits

input                            TD_HS;                                                            //          TV Decoder H_SYNC

input                            TD_VS;                                                            //          TV Decoder V_SYNC

output                          TD_RESET;                                         //          TV Decoder Reset

////////////////////////            GPIO   ////////////////////////////////

inout    [35:0]    GPIO_0;                                                           //          GPIO Connection 0

inout    [35:0]    GPIO_1;                                                           //          GPIO Connection 1

 

//////////////////////////////////////////////////////////////////////

////////////////////////////////////

//DLA state machine variables

wire reset;

reg [17:0] addr_reg; //memory address register for SRAM

reg [15:0] data_reg; //memory data register  for SRAM

reg we ;             //write enable for SRAM

reg [3:0] sum; //neighbor sum

reg lock; //did we stay in sync?

reg memwait; //slow mem?

////////////////////////////////////////

///////////////////////////////////////////////////////////////////////

 

//          LCD ON

assign   LCD_ON                      =          1'b0;

assign   LCD_BLON      =          1'b0;

 

//          All inout port turn to tri-state

assign   DRAM_DQ                   =          16'hzzzz;

assign   FL_DQ             =          8'hzz;

assign   SRAM_DQ                   =          16'hzzzz;

assign   OTG_DATA     =          16'hzzzz;

assign   SD_DAT                       =          1'bz;

assign   ENET_DATA    =          16'hzzzz;

assign   GPIO_0                        =          36'hzzzzzzzzz;

assign   GPIO_1                        =          36'hzzzzzzzzz;

 

wire [31:0]         mSEG7_DIG;

reg        [31:0]   Cont;

wire                  VGA_CTRL_CLK;

wire                  AUD_CTRL_CLK;

wire [9:0]           mVGA_R;

wire [9:0]           mVGA_G;

wire [9:0]           mVGA_B;

wire [19:0]         mVGA_ADDR;                          //video memory address

wire [9:0]  Coord_X, Coord_Y;    //display coods

wire                  DLY_RST;

 

assign   TD_RESET      =          1'b1;     //          Allow 27 MHz input

//assign AUD_ADCLRCK           =          AUD_DACLRCK;

//assign AUD_XCK                    =          AUD_CTRL_CLK;

 

 

 

Reset_Delay                               r0         (           .iCLK(CLOCK_50),.oRESET(DLY_RST)           );

 

VGA_Audio_PLL                      p1        (           .areset(~DLY_RST),.inclk0(CLOCK_27),.c0(VGA_CTRL_CLK),.c1(AUD_CTRL_CLK),.c2(VGA_CLK)      );

 

 

VGA_Controller                        u1        (           //          Host Side

                                                                                    .iCursor_RGB_EN(4'b0111),

                                                                                    .oAddress(mVGA_ADDR),

                                                                                    .oCoord_X(Coord_X),

                                                                                    .oCoord_Y(Coord_Y),

                                                                                    .iRed(mVGA_R),

                                                                                    .iGreen(mVGA_G),

                                                                                    .iBlue(mVGA_B),

                                                                                    //          VGA Side

                                                                                    .oVGA_R(VGA_R),

                                                                                    .oVGA_G(VGA_G),

                                                                                    .oVGA_B(VGA_B),

                                                                                    .oVGA_H_SYNC(VGA_HS),

                                                                                    .oVGA_V_SYNC(VGA_VS),

                                                                                    .oVGA_SYNC(VGA_SYNC),

                                                                                    .oVGA_BLANK(VGA_BLANK),

                                                                                    //          Control Signal

                                                                                    .iCLK(VGA_CTRL_CLK),

                                                                                    .iRST_N(DLY_RST)      );

 

 

// SRAM_control

assign SRAM_ADDR = addr_reg;

assign SRAM_DQ = (we)? 16'hzzzz : data_reg ;

assign SRAM_UB_N = 0;                                                           // hi byte select enabled

assign SRAM_LB_N = 0;                                                           // lo byte select enabled

assign SRAM_CE_N = 0;                                                           // chip is enabled

assign SRAM_WE_N = we;                                                        // write when ZERO

assign SRAM_OE_N = 0;                                                           //output enable is overidden by WE

 

//new r,g,b business

 

assign  mVGA_R =

{(xi_hold_reg == 2'b00 ? SRAM_DQ[15] :

 xi_hold_reg == 2'b01 ? SRAM_DQ[11] :

 xi_hold_reg == 2'b10 ? SRAM_DQ[7] :

 xi_hold_reg == 2'b11 ? SRAM_DQ[3] :

 1'b0), 9'b0};

 

assign  mVGA_G =

{(xi_hold_reg == 2'b00 ? SRAM_DQ[14:13] :

 xi_hold_reg == 2'b01 ? SRAM_DQ[10:9] :

 xi_hold_reg == 2'b10 ? SRAM_DQ[6:5] :

 xi_hold_reg == 2'b11 ? SRAM_DQ[2:1] :

 2'b0), 8'b0} ;

 

assign  mVGA_B =

{(xi_hold_reg == 2'b00 ? SRAM_DQ[12] :

 xi_hold_reg == 2'b01 ? SRAM_DQ[8] :

 xi_hold_reg == 2'b10 ? SRAM_DQ[4] :

 xi_hold_reg == 2'b11 ? SRAM_DQ[0] :

 1'b0), 9'b0} ;

 

 

 

 

 

always @ (posedge VGA_CTRL_CLK)

            begin

             xi_hold_reg <= {Coord_X[0],Coord_Y[0]};

            end

 

// define reset

assign reset = ~KEY[0];

 

//write statement to execture simple L system- W:F-F-F-F, P: F->F-F+F+FF-F-F+F

reg [1:0] turtle_count;

reg [4:0] update_F_count;          

reg [5:0] axiom_count;

reg [3:0] turtle_direction;

reg [9:0] x_position;

reg [9:0] y_position;

 

//variables

reg FF_Done; //allows FF to be visit twice to execute FF

reg FF_Done_sub;

reg FF_Done_sub_1;

reg finished_a_production; //flag for indicated an entire production was executed

reg finished_sub_production_0; //flag for indicated an entire sub_production was executed

reg finished_sub_production_1; //flag for indicated an entire sub_production was executed

reg finished_sub_production_2; //flag for indicated an entire sub_production was executed

 

 

//state variables

reg [5:0] axiom_state;

reg [5:0] production;

reg [5:0] sub_production_0;

reg [5:0] sub_production_1;

reg [5:0] sub_production_2;

 

reg [5:0] production_state;

reg [5:0] sub_production_0_state;

reg [5:0] sub_production_1_state;

reg [5:0] sub_production_2_state;

 

reg [3:0] hold_turtle_direction_bracket;

reg [8:0] hold_x_position_bracket;

reg [8:0] hold_y_position_bracket;

 

reg [3:0] sub_0_hold_turtle_direction_bracket;

reg [8:0] sub_0_hold_x_position_bracket;

reg [8:0] sub_0_hold_y_position_bracket;

 

reg [3:0] sub_1_hold_turtle_direction_bracket;

reg [8:0] sub_1_hold_x_position_bracket;

reg [8:0] sub_1_hold_y_position_bracket;

 

reg [3:0] sub_2_hold_turtle_direction_bracket;

reg [8:0] sub_2_hold_x_position_bracket;

reg [8:0] sub_2_hold_y_position_bracket;

 

 

 

//debugging variable

reg arrived_flag;

reg arrived_flag_1;

 

 

//hold variables

reg [5:0] production_hold;

reg [5:0] sub_production_0_hold;

reg [5:0] sub_production_1_hold;

reg [5:0] sub_production_2_hold;

 

//other

reg sub_pixel_count;

reg [1:0] xi_reg;

reg [1:0] xi_hold_reg;

reg f_count_flag;

 

//

reg [3:0] delta_green;

reg [3:0] delta_red;

 

//state names for top level axiom_state statemachine

parameter  plant_a_seed = 6'd0 , axiom_0 = 6'd1, axiom_1 = 6'd2, axiom_2 = 6'd3,

                           axiom_3 = 6'd4, execute_production =6'd5 , axiom_last= 6'd6, execute_sub_production_0 = 6'd7,

                           execute_sub_production_1 = 6'd8, execute_sub_production_2 = 6'd9;

                          

//state names for turtle direction; simple counter to keep track of direction                

parameter  up = 2'b00, right = 2'b01, down = 2'b10, left = 2'b11 ;                          

 

 

//debug stuff

assign LEDG[0] = arrived_flag;

assign LEDG[1] = arrived_flag_1;

 

 

//stochastic stuff

//wire [30:0] rand_out;

//reg [30:0] rand_reg;

 

 

//Rand blah (

//.iClk(CLOCK_50),

//.iReset(reset),

//.xRand(rand_out)

//);

 

 

//assign LEDR[2:0] = rand_reg[2:0];

 

//always @ (posedge KEY[2])

//begin

//rand_reg <= rand_out;

//end                                        

 

//end stochastic stuff for now

 

 

 

 

 

always @ (posedge VGA_CTRL_CLK)

begin//begin always block

 

if (reset)           

            begin

                        //turn over the soil

                        addr_reg <=  {Coord_X[9:1],Coord_Y[9:1]} ;        // [17:0]

                        we <= 1'b0;                            //write some memory

                        data_reg <= 16'b0;                     //write all zeros (black)

                        //data_reg <= 16'hFFFF;                        //write all zeros (black)

                       

                        //init counters and state variables

                        production <= 6'd0;

                        sub_production_0 <= 6'd0;

                        sub_production_1 <= 6'd0;

                        sub_production_2 <= 6'd0;

                       

                        production_state <= 6'd0;

                        sub_production_0_state <= 6'd0;

                        sub_production_1_state <= 6'd0;

                        sub_production_2_state <= 6'd0;

                       

                       

                        //initialize end production flags

                        finished_a_production <= 1'b0;

                        finished_sub_production_0 <= 1'b0;

                        finished_sub_production_1 <= 1'b0;

                        finished_sub_production_2 <= 1'b0;

                       

                       

                        arrived_flag <= 1'b0;

                        arrived_flag_1 <= 1'b0;

                       

                        hold_x_position_bracket<= 6'd0;

                        hold_y_position_bracket<= 6'd0;

                       

                        sub_0_hold_turtle_direction_bracket <= 6'd0;

                        sub_0_hold_x_position_bracket <= 6'd0;

                        sub_0_hold_y_position_bracket <= 6'd0;

                       

                        sub_1_hold_turtle_direction_bracket <= 6'd0;

                        sub_1_hold_x_position_bracket <= 6'd0;

                        sub_1_hold_y_position_bracket <= 6'd0;

                       

                        sub_2_hold_turtle_direction_bracket <= 6'd0;

                        sub_2_hold_x_position_bracket <= 6'd0;

                        sub_2_hold_y_position_bracket <= 6'd0;

                       

                       

                        production_hold <= 6'd0;

                        sub_production_0_hold <= 6'd0;

                        sub_production_1_hold <= 6'd0;

                        sub_production_2_hold <= 6'd0;

                       

                        turtle_count <= 2'd0;

                       

                        delta_green <= 4'b1111;

                        delta_red <= 4'b0000;

           

                        update_F_count <= 5'd0;

                        FF_Done<= 1'b0;

                        FF_Done_sub <= 1'b0;

                        FF_Done_sub_1 <= 1'b0;

                        turtle_direction = 2'd0;//set initial direction of turtle to face up

                       

                        axiom_count <= 6'd1;

                        axiom_state <= plant_a_seed;

                       

                       

           

            end //end reset

 

 

////////////////////

           

 

 

           

           

else if ((~VGA_VS | ~VGA_HS) & KEY[3]) 

            begin//begin else if

            lock <= 1'b1;                            

            case(axiom_state)

           

                        plant_a_seed: //plant a seed on the screen. for now it will be a set position

                                    begin

                                    //addr_reg <= {9'd99, 9'd240};//(x,y)

                                    //we <= 1'b0;     //write memory                                                                          

                                    //data_reg <=  16'b0000111100000000;//make start dot green         

                                    //put starting point in x,y position variable for soon future use

                                    //x_position<= 9'd100;

                                    //y_position<= 9'd240;

                                    //axiom_state <= axiom_0;

                                   

                                    addr_reg <= {x_position[9:1], y_position[9:1]};

                                   

                                    we <= 1'b0;       //write memory                                                                          

                                    data_reg <=  16'b0000111100000000;//make start dot green           

                                    //put starting point in x,y position variable for soon future use

                                    x_position<= 9'd200;

                                    y_position<= 9'd508;

                                     

                                    axiom_state <= axiom_0;

                                   

                                    end      

 

                        //now execute_L_system:

                        //axiom variable must be initialized to 0 at reset

                        axiom_0://F of [F-F-F-F] axiom

                                    begin

                                   

 

                                    axiom_count <=  6'd10; //axiom_count +1;//set axiom_count = 2

                                    axiom_state <= execute_production;

                                    production<= 6'd1;

                                    //turtle_direction <= turtle_direction+1;

                                    end      

                                   

                       

                       

                       

                        10:

                                    begin

                                    //empty state

                                    end

 

 

 

                        execute_production:

                       

                                                            begin//begin IF statement to execute production string F->F-F+F+FF-F-F+F

                                                                       

                                                                                    case(production)

                                                                                   

                                                                                    0://F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                production_hold <= production_hold +1;

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;

                                                                                                end

                                                                                   

                                                                                    1://F

                                                                                   

                                                                                      //FF . . of . . FF-[-F+F+F]+[+F-F-F]      

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                production_hold <= production_hold +2;

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;

                                                                                                end

                                                                                   

                                                                                    2://-

                                                                                   

                                                                                      //FF- . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //arrived

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                production <= 6'd3;

                                                                                                arrived_flag_1 <= 1'b1;

                                                                                                end

                                                                                   

                                                                                    3://[

                                                                                      //FF-[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                //arrived

                                                                                                hold_turtle_direction_bracket <= turtle_direction;

                                                                                                hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                hold_y_position_bracket <= y_position;//for later retrival

                                                                                                production <= 6'd4;

                                                                                                end      

                                                                                               

                                                                                    4://-F

                                                                                   

                                                                                      //FF-[-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //arrived

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                production_hold <= production_hold +3;//add to to account for 2 brackets

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;

                                                                                                end      

                                                                                               

                                                                                               

                                                                                    5://+F

                                                                                      //FF-[-F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //arrived

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                production_hold <= production_hold + 1;//add two to account for missed production

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;                       //update in previous state

                                                                                                end

                                                                                               

                                                                                               

                                                                                    6://+F

                                                                                      //FF-[-F+F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //got here too

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                production_hold <= production_hold + 1;//add two to account for missed production

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;                       //update in previous state

                                                                                                delta_green<= 4'b1010;

                                                                                                end

                                                                                               

                                                                                    7://do close bracket. . . .]. . . i.e. load back turtle_dir and x,y values. . .

                                                                                      //FF-[-F+F+F] . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //c'est arrive ici arrived_flag_1 <= 1'b1;///???????????????????????????????????;)

                                                                                                turtle_direction <= hold_turtle_direction_bracket;//

                                                                                                x_position <= hold_x_position_bracket;//load values back from storage registers

                                                                                                y_position<= hold_y_position_bracket;//for later retrival//production_hold <= production_hold + 1;

                                                                                                production <= 6'd8;

                                                                                                end

                                                                                               

                                                                                    8://+

                                                                                      //FF-[-F+F+F]+ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                production <= 6'd9;

                                                                                                end

                                                                                               

                                                                                               

                                                                                    9://[

                                                                                      //FF-[-F+F+F]+[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                hold_turtle_direction_bracket <= turtle_direction;

                                                                                                hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                hold_y_position_bracket <= y_position;//for later retrival

                                                                                                //production <= production +1;//keep counting scheme going for simplicity

                                                                                                production <= 6'd10;

                                                                                                end

                                                                                               

                                                                                    10://+F

                                                                                       //FF-[-F+F+F]+[+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                production_hold <= production_hold + 4;//add two to account for missed production

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;                       //update in previous state

                                                                                                end

                                                                                               

                                                                                    11://-F

                                                                                       //FF-[-F+F+F]+[+F-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                delta_green<= 4'b1100; //GGGGGGGGGGGGGGGGGGGGGG

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                production_hold <= production_hold + 1;//add to to account for 2 brackets

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                //production_state<=6'd1;

                                                                                                end      

                                                                                               

                                                                                    12://-F

                                                                                       //FF-[-F+F+F]+[+F-F-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                production_hold <= production_hold +1;//add to to account for 2 brackets

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                delta_green<= 4'b1111;

                                                                                                //delta_red <= 4'b1100;

                                                                                                //production_state<=6'd1;

                                                                                                end

                                                                                               

                                                                                    13://]

                                                                                       //do close bracket. . . .]. . . i.e. load back turtle_dir and x,y values. . .

                                                                                       //FF-[-F+F+F]+[+F-F-F] . . of . . FF-[-F+F+F]+[+F-F-F] 

                                                                                                begin

                                                                                                turtle_direction <= hold_turtle_direction_bracket;//

                                                                                                x_position <= hold_x_position_bracket;//load values back from storage registers

                                                                                                y_position<= hold_y_position_bracket;//for later retrival

                                                                                                finished_a_production <= 1'b1;//throw finish production flag

                                                                                                //gets here

                                                                                                axiom_state <= execute_sub_production_0;

                                                                                                end

                                                                                               

                                                                                    endcase

                                                                                   

                                                                        end//end state 0

 

                        execute_sub_production_0:

                       

                                                            begin//begin IF statement to execute production string F->F-F+F+FF-F-F+F

                                                                       

                                                                                    case(sub_production_0)

                                                                                   

                                                                                    0://F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                sub_production_0_hold <= sub_production_0_hold +1;

                                                                                                axiom_state <= execute_sub_production_1;

                                                                                                end

                                                                                               

                                                                                               

                                                                                    1://F

                                                                                   

                                                                                      //FF . . of . . FF-[-F+F+F]+[+F-F-F]      

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                sub_production_0_hold <= sub_production_0_hold +1;

                                                                                                axiom_state <= execute_sub_production_1;

                                                                                                end

                                                                                   

                                                                                    2://-

                                                                                   

                                                                                      //FF- . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_0 <= 6'd3;

                                                                                                end

                                                                                   

                                                                                    3://[

                                                                                      //FF-[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                sub_0_hold_turtle_direction_bracket <= turtle_direction;

                                                                                                sub_0_hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                sub_0_hold_y_position_bracket <= y_position;//for later retrival

                                                                                                sub_production_0 <= 6'd4;

                                                                                                end      

                                                                                               

                                                                                    4://-F

                                                                                   

                                                                                      //FF-[-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_0_hold <= sub_production_0_hold +3;//add to to account for 2 brackets

                                                                                                axiom_state <= execute_sub_production_1;

                                                                                               

                                                                                                end      

                                                                                               

                                                                                               

                                                                                    5://+F

                                                                                      //FF-[-F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_0_hold <= sub_production_0_hold + 1;//add two to account for missed production

                                                                                                axiom_state <= execute_sub_production_1;                      //update in previous state

                                                                                                end

                                                                                               

                                                                                               

                                                                                    6://+F

                                                                                      //FF-[-F+F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_0_hold <= sub_production_0_hold + 1;//add two to account for missed production

                                                                                                axiom_state <= execute_sub_production_1;                      //update in previous state

                                                                                                end

                                                                                               

                                                                                                //good until here. . .

                                                                                               

                                                                                    7://do close bracket. . . .]. . . i.e. load back turtle_dir and x,y values. . .

                                                                                      //FF-[-F+F+F] . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= sub_0_hold_turtle_direction_bracket;//

                                                                                                x_position <= sub_0_hold_x_position_bracket;//load values back from storage registers

                                                                                                y_position<= sub_0_hold_y_position_bracket;//for later retrival//production_hold <= production_hold + 1;

                                                                                                sub_production_0 <= 6'd8;

                                                                                                end

                                                                                               

                                                                                    8://+

                                                                                      //FF-[-F+F+F]+ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_0 <= 6'd9;

                                                                                                end

                                                                                               

                                                                                               

                                                                                    9://[

                                                                                      //FF-[-F+F+F]+[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                sub_0_hold_turtle_direction_bracket <= turtle_direction;

                                                                                                sub_0_hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                sub_0_hold_y_position_bracket <= y_position;//for later retrival

                                                                                                //production <= production +1;//keep counting scheme going for simplicity

                                                                                                sub_production_0 <= 6'd10;

                                                                                                end

                                                                                               

                                                                                    10://+F

                                                                                       //FF-[-F+F+F]+[+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_0_hold <= sub_production_0_hold + 4;//add two to account for missed production

                                                                                                axiom_state <= execute_sub_production_1;                      //update in previous state

                                                                                                end

                                                                                               

                                                                                    11://-F

                                                                                       //FF-[-F+F+F]+[+F-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_0_hold <= sub_production_0_hold + 1;//add to to account for 2 brackets

                                                                                                axiom_state <= execute_sub_production_1;

                                                                                                end      

                                                                                                 //good to here

                                                                                    12://-F

                                                                                       //FF-[-F+F+F]+[+F-F-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_0_hold <= sub_production_0_hold +1;//add to to account for 2 brackets

                                                                                                axiom_state <= execute_sub_production_1;

                                                                                                end

                                                                                               

                                                                                    13://]

                                                                                       //do close bracket. . . .]. . . i.e. load back turtle_dir and x,y values. . .

                                                                                       //FF-[-F+F+F]+[+F-F-F] . . of . . FF-[-F+F+F]+[+F-F-F] 

                                                                                                begin

                                                                                                turtle_direction <= sub_0_hold_turtle_direction_bracket;//

                                                                                                x_position <= sub_0_hold_x_position_bracket;//load values back from storage registers

                                                                                                y_position<= sub_0_hold_y_position_bracket;//for later retrival

                                                                                                //production <= production +1;

                                                                                                //production <= 6'd4;

                                                                                                finished_sub_production_0 <= 1'b1;//throw finish production flag

                                                                                                axiom_state <= execute_sub_production_1;

                                                                                                end

                                                                                               

                                                                                    endcase

                                                                                   

                                                                        end//end state 0

 

 

                        execute_sub_production_1:

                       

                                                                       

                                                //if(finished_a_production==0)//if finished_a_production flag not thrown, go. .

                                                            begin//begin IF statement to execute production string F->F-F+F+FF-F-F+F

                                                                       

                                                                                    case(sub_production_1)

                                                                                   

                                                                                    0://F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                sub_production_1_hold <= sub_production_1_hold +1;

                                                                                                //sub_production_1_state<=6'd1;

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                end

                                                                                               

                                                                                               

                                                                                    1://F

                                                                                   

                                                                                      //FF . . of . . FF-[-F+F+F]+[+F-F-F]      

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                sub_production_1_hold <= sub_production_1_hold +1;

                                                                                                //sub_production_1_state<=6'd1;

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                end

                                                                                   

                                                                                    2://-

                                                                                   

                                                                                      //FF- . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_1 <= 6'd3;

                                                                                                end

                                                                                   

                                                                                    3://[

                                                                                      //FF-[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                sub_1_hold_turtle_direction_bracket <= turtle_direction;

                                                                                                sub_1_hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                sub_1_hold_y_position_bracket <= y_position;//for later retrival

                                                                                                sub_production_1 <= 6'd4;

                                                                                                end      

                                                                                               

                                                                                    4://-F

                                                                                   

                                                                                      //FF-[-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_1_hold <= sub_production_1_hold +3;//add to to account for 2 brackets

                                                                                                //sub_production_1_state<=6'd1;

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                end      

                                                                                               

                                                                                               

                                                                                    5://+F

                                                                                      //FF-[-F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_1_hold <= sub_production_1_hold + 1;//add two to account for missed production

                                                                                                //sub_production_1_state<=6'd1;                        //update in previous state

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                end

                                                                                               

                                                                                               

                                                                                    6://+F

                                                                                      //FF-[-F+F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_1_hold <= sub_production_1_hold + 1;//add two to account for missed production

                                                                                                //sub_production_1_state<=6'd1;                        //update in previous state

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                               

                                                                                                end

                                                                                               

                                                                                                //good until here. . .

                                                                                               

                                                                                    7://do close bracket. . . .]. . . i.e. load back turtle_dir and x,y values. . .

                                                                                      //FF-[-F+F+F] . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= sub_1_hold_turtle_direction_bracket;//

                                                                                                x_position <= sub_1_hold_x_position_bracket;//load values back from storage registers

                                                                                                y_position<= sub_1_hold_y_position_bracket;//for later retrival//production_hold <= production_hold + 1;

                                                                                                sub_production_1 <= 6'd8;

                                                                                                end

                                                                                               

                                                                                    8://+

                                                                                      //FF-[-F+F+F]+ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_1 <= 6'd9;

                                                                                                end

                                                                                               

                                                                                               

                                                                                    9://[

                                                                                      //FF-[-F+F+F]+[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                sub_1_hold_turtle_direction_bracket <= turtle_direction;

                                                                                                sub_1_hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                sub_1_hold_y_position_bracket <= y_position;//for later retrival

                                                                                                //production <= production +1;//keep counting scheme going for simplicity

                                                                                                sub_production_1 <= 6'd10;

                                                                                                end

                                                                                               

                                                                                    10://+F

                                                                                       //FF-[-F+F+F]+[+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_1_hold <= sub_production_1_hold + 4;//add two to account for missed production

                                                                                                //sub_production_1_state<=6'd1;                        //update in previous state

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                end

                                                                                               

                                                                                    11://-F

                                                                                       //FF-[-F+F+F]+[+F-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_1_hold <= sub_production_1_hold + 1;//add to to account for 2 brackets

                                                                                                //sub_production_1_state<=6'd1;

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                //finished_a_production <= 1'b1;//throw finish production flag

                                                                                                end      

                                                                                                 //good to here

                                                                                    12://-F

                                                                                       //FF-[-F+F+F]+[+F-F-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_1_hold <= sub_production_1_hold +1;//add to to account for 2 brackets

                                                                                                //sub_production_1_state<=6'd1;

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                //finished_sub_production_0 <= 1'b1;//throw finish production flag

                                                                                                end

                                                                                               

                                                                                    13://]

                                                                                       //do close bracket. . . .]. . . i.e. load back turtle_dir and x,y values. . .

                                                                                       //FF-[-F+F+F]+[+F-F-F] . . of . . FF-[-F+F+F]+[+F-F-F] 

                                                                                                begin

                                                                                                turtle_direction <= sub_1_hold_turtle_direction_bracket;//

                                                                                                x_position <= sub_1_hold_x_position_bracket;//load values back from storage registers

                                                                                                y_position<= sub_1_hold_y_position_bracket;//for later retrival

                                                                                                //production <= production +1;

                                                                                                //production <= 6'd4;

                                                                                                finished_sub_production_1 <= 1'b1;//throw finish production flag

                                                                                                //sub_production_1_state<=6'd1;

                                                                                                axiom_state <= execute_sub_production_2;

                                                                                                end

                                                                                               

                                                                                    endcase

                                                                                   

                                                                       

                                                end//end execute_production_1                          

           

                                    execute_sub_production_2:

                       

                                    //want to execute FF-[-F+F+F]+[+F-F-F]

                                   

                                    begin//begin execute_production

                                     case(sub_production_2_state)//begin production case statement

                                               

                                                0://production_state #0 - execute_rule

                                                //begin //begin state 0

                                                                       

                                                //if(finished_a_production==0)//if finished_a_production flag not thrown, go. .

                                                            begin//begin IF statement to execute production string F->F-F+F+FF-F-F+F

                                                                       

                                                                                    case(sub_production_2)

                                                                                   

                                                                                    0://F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                sub_production_2_hold <= sub_production_2_hold +1;

                                                                                                sub_production_2_state<=6'd1;

                                                                                                //arrived here

                                                                                                end

                                                                                               

                                                                                               

                                                                                    1://F

                                                                                   

                                                                                      //FF . . of . . FF-[-F+F+F]+[+F-F-F]      

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                sub_production_2_hold <= sub_production_2_hold +1;

                                                                                                sub_production_2_state<=6'd1;

                                                                                                end

                                                                                   

                                                                                    2://-

                                                                                   

                                                                                      //FF- . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      //due to nature of this, do change direction as own state 

                                                                                                begin

                                                                                                //no update of turtle direction as turtle starts with default or last direction

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_2 <= 6'd3;

                                                                                                end

                                                                                   

                                                                                    3://[

                                                                                      //FF-[ . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                      // do open bracket. . . [ . . . i.e. store turtle_dir and x,y values. . .

                                                                                                begin

                                                                                                sub_2_hold_turtle_direction_bracket <= turtle_direction;

                                                                                                sub_2_hold_x_position_bracket <= x_position;//load/store values into storage registers

                                                                                                sub_2_hold_y_position_bracket <= y_position;//for later retrival

                                                                                                sub_production_2 <= 6'd4;

                                                                                                end      

                                                                                               

                                                                                    4://-F

                                                                                   

                                                                                      //FF-[-F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction+1;

                                                                                                sub_production_2_hold <= sub_production_2_hold +3;//add to to account for 2 brackets

                                                                                                sub_production_2_state<=6'd1;

                                                                                               

                                                                                                end      

                                                                                               

                                                                                               

                                                                                    5://+F

                                                                                      //FF-[-F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_2_hold <= sub_production_2_hold + 1;//add two to account for missed production

                                                                                                sub_production_2_state<=6'd1;              //update in previous state

                                                                                                end

                                                                                               

                                                                                               

                                                                                    6://+F

                                                                                      //FF-[-F+F+F . . of . . FF-[-F+F+F]+[+F-F-F]

                                                                                                begin

                                                                                                turtle_direction <= turtle_direction-1;

                                                                                                sub_production_2_hold <= sub_production_2_hold + 1;//add two to account for missed production

                                                                                                sub_production_2_state<=6'd1;              //update in previous state

                                                                                               

                                                                                               

                                                                                                end

                                                                                               

                                                                                                //good until here. . .

                                                                                               

                                                             &nb