//SPI example using AD7303 DAC from Analog Devices
//set DAC for simultaneous update of two channels
// Mega644 GCC
//
//connect MOSI B.5 to DIN on AD7303
//connect SCLK B.7 to SCLK on AD7303
//connect B.4 to notSYNC on the AD7303

#include <inttypes.h>
#include <avr/io.h>
#include <util/delay.h>

#define begin {
#define end }

// bit handling macros for i/o registers
#define READ(U, N) ((U) >> (N) & 1u)
#define SET(U, N) ((void)((U) |= 1u << (N)))
#define CLR(U, N) ((void)((U) &= ~(1u << (N))))
#define FLIP(U, N) ((void)((U) ^= 1u << (N)))

// AD7303 control words
uint8_t DAC_cntl_1, DAC_cntl_2;

// DDS accumulator and increment
uint8_t DDSacc, DDSinc;

// throwaway variable 
// not used since DAC does not return any data
uint8_t junk ;

int main(void)
begin

	DDSinc = 16; //sawtooth DDS rate
    
    //set up i/o data direction
    //DDRB.4 = 1; //output chip select for DAC (notSYNC)
    //DDRB.5 = 1; //output MOSI 
    //DDRB.6 = 0; //input MISO is not used by the DAC
    //DDRB.7 = 1; //output SCLK   
	DDRB = (1<<DDB4) | (1<<DDB5) | (1<<DDB7) ; 
	// initialize notSYNC
	SET(PORTB,4) ;

	//set up SPI control register SPCR
    //bit 7 SPIE=0 no ISR
    //bit 6 SPE=1 enable spi
    //bit 5 DORD=0 msb first 
    //bit 4 MSTR=1 Mega32 is spi master
    //bit 3 CPOL=1 clock polarity
    //bit 2 CPHA=1 clock phase
    //bit 1,0 rate sel=00 along with SPSR.0=1 sets clk to f/2 = 8 MHz
	SPCR = (1<<SPE) | (1<<MSTR) | (1<<CPOL) | (1<<CPHA) ; //SPCR = 0b01011100 ;                                                                               
    SPSR = (1<<SPI2X) ; //SPSR = 1; 
    
    //DAC control word (specific to AD7303)
    // bit 7 notINT/EXT set to notINT = 0. Use internal Vref
    // bit 6 = 0
    // bit 5 LDAC load and update both channels when set
    // bit 4 PDB = 0 pwer down channel B
    // bit 3 PDA = 0 pwer down channel A
    // bit 2 notA/B = 0 chooses A
    // bit 1 CR1=0  control bits modify load mode
    // bit 0 CR0=1  set to load A from SR
	// The actual commands:
    // command to: Load A from shift register
    DAC_cntl_1 = 0b00000001 ; 
    // command to: Load B from SR and and update both outputs
    DAC_cntl_2 = 0b00100100 ;

    while (1)
    begin
		
		//SYNC low begins load for the AD7303  
        CLR(PORTB,4) ; 
		//set DAC parameters               
        SPDR = DAC_cntl_1;        
		//wait until SPIF is set (SPI done)
        while (!(SPSR & (1<<SPIF))) ;
		junk = SPDR ;
		//send channel A
        SPDR = DDSacc ;  
		//wait until SPIF is set (SPI done)
        while (!(SPSR & (1<<SPIF))) ;
		junk = SPDR ;
		//SYNC high ends load for the AD7303
        SET(PORTB,4) ;              

		//SYNC low begins load for the AD7303 
        CLR(PORTB,4) ; 
		//set DAC parameters              
        SPDR = DAC_cntl_2;       
		//wait until SPIF is set (SPI done) 
        while (!(SPSR & (1<<SPIF))) ;
		junk = SPDR ;
		//send channel B
        SPDR = DDSacc+128 ;      
		//wait until SPIF is set (SPI done)
        while (!(SPSR & (1<<SPIF))) ;
		junk = SPDR ;
		//SYNC high ends load for the AD7303
        SET(PORTB,4) ;              
     	    
        DDSacc = DDSacc + DDSinc;  // sawtooth generator    
    end
end