#include <Mega32.h>
#include <delay.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
                  
#define adMux_LR	0b11100000 //Define ADMUX register for Left_Right reading
#define adMux_UD	0b11100001 //Define ADMUX register for Up and down reading
#define T1	50  //Define task1 timer0 interval of execution 


unsigned char c, c_high, c_low, c_trans, t1, leftRight, state;
unsigned char lowerLimitLR, UpperLimitLR,bandwidthLR;
unsigned char lowerLimitUD, UpperLimitUD,bandwidthUD;



//************************************************************************
interrupt [TIM0_COMP] void timer0_compare(void) {
       if(t1 > 0) t1--;
}

//************************************************************************
void getADC(void) {
	t1=T1;
	c = ADCH;
		
    	if (leftRight) {
		//lower values left and higher values right
		if (c <= 79)
			c_high = 0x10;
		else if (99 >= c && c >= 80)  
			c_high = 0x40;
		else if (110 >= c && c >= 100)
			c_high = 0x70;
		else if (135 >= c && c >= 111)  
			c_high = 0x90;
		else if (c >= 136)  
			c_high = 0xc0;

			
        ADMUX = adMux_UD;
	}else {
	     if (c <= 99)  
			c_low = 0x01;
		else if (119>= c && c >= 100)  
			c_low = 0x04;
		else if (130 >= c && c >= 120)
			c_low = 0x07;
		else if (155 >= c && c >= 131)  
			c_low = 0x09;
		else if (c >= 156)  
			c_low = 0x0c;
			
		ADMUX = adMux_LR;
	}
	
	ADCSR = 0b11000110;
	leftRight = leftRight^1;
	c_trans = c_high | c_low;
	
	
	
}

//************************************************************************
void main(void)
{
	//set up the ports
	DDRA=0x00;	// PORT A is an input
	DDRD=0x00;  // PORT D is an input
	DDRC=0xff;	// PORT C is an output
	DDRB=0xff;	// PORT B is an output
	PORTC=0xff;
	PORTB = 0xff;
	
	//ADC init
	ADMUX = adMux_LR;	//AVcc for reference, ADLAR, PortA.0
	ADCSR = 0b11000110;	//AD enable, AD start, prescale 1/64
	
	//set up timer 0  
   	TIMSK = 2;       	//turn on timer 0 cmp match ISR 
   	OCR0 = 250;         //set the compare re to 250 time ticks
 	TCCR0=0b00001011;   //prescalar to 64 and turn on clear-on-match
     
   	//Setup UART based transmisson
   	UCSRB = 0x08; 		//TxD   (PORTD.1 
	UBRRL = 207;		//103 = Clk/(clk*BaudRate -1) = 16e6/(16*9600-1)
	
	t1 = T1;
	leftRight = 1;
	 
	//crank up the ISRs
	#asm
	
  		sei
  		
	#endasm
	
	while (1) {
		if (t1 == 0) getADC();
	
		if (c_trans == 0x77) {	//Tranmsit pluse signal to error correct reciever
			PORTB.0 = 1;
			putchar(0xaa);
			putchar(0xaa);
			putchar(0xaa);
			putchar(0xaa);
			putchar(0xaa);
			putchar(0xaa);
			state = 0;
		} else {
			PORTB.0 = 0;
			putchar(c_trans);
			state = state++;
		 	if (state == 5) {	//Tranmsit pluse signal to initialize reciever
				putchar(0xaa);
				state = 0;	
			}
		}
		
	  };
}