;Ameer Ali & Paul Lahham
;EE476	Final Project - Hummer Transmitter

.nolist
.include "c:\avrtools\appnotes\8535def.inc"
.list

.def	save	=r1	;SREG temp reg
.def	temp	=r16	;temporary register
.def	AnaLo	=r17	;A to D result
.def	AnaHi	=r18
.def	opcode	=r19
.def	sendcode =r20
	
.equ	samp_rate = 500		;sample and send every 1000 milliseconds (up to 4194)
.equ	baud12	=207		;1200 baud rate for wireless transmission

.equ	init_code = 0b10010000

; *** MACROS ***

; Set OCR1A using sampling rate
.MACRO SET_OCR1A
	ldi	temp, HIGH((@0*1000)/64)
	out	OCR1AH, temp
	ldi	temp, LOW((@0*1000)/64)
	out	OCR1AL, temp
.ENDMACRO

;Returns opcode for given channel in top nibble of AnaLo
.MACRO	GET_OPCODE
	
	in	AnaLo, ADCL
	in	AnaHi, ADCH

	lsr	AnaHi
	ror	AnaLo
	lsr	AnaHi
	ror	AnaLo
	
	ldi	temp, 0b01111000

	sbrs	AnaLo, 7	 ;if bit 7 is off
	eor	AnaLo, temp	 ;flip bits 5,6
	
	andi	AnaLo, 0b11111000	

.ENDMACRO

;***** Initialization
.cseg
.org $0000
	rjmp 	RESET	;reset entry vector
	reti		
	reti
	reti
	reti
	reti	
	rjmp	t1match
	reti
	reti
	reti
	reti		
	reti
	reti
	reti 	 
	reti
	reti
	reti
	

RESET:	ldi	temp, LOW(RAMEND) ;setup stack pointer
	out 	SPL, temp
	ldi	temp, HIGH(RAMEND)
	out	SPH, temp

	;set up port B to run LEDS
	ser	temp		;set PORTB to be
	out	DDRB,temp	;all outputs to LEDs
	out	PORTB, temp

	;enable TX and set baud rate at 1200
	ldi	temp, 0b00001000
	out	UCR, temp
	ldi	temp, baud12
	out	UBRR, temp
	
	;set up Timer 1 to interrupt on compare A match
	;and set the compare time to 62500 ticks
	ldi	temp,0b00010000	;enable t1 matchA interrupt
	out	TIMSK, temp

	SET_OCR1A	samp_rate

	ldi 	temp,0b00001100	;prescale timer by 256 (one tick=64 microsec)
	out 	TCCR1B, temp	;and clear-on-matchA

	;enable analog converter and set at 125kHz
	ldi	temp, 0b10000101
	out	ADCSR, temp

	clr	sendcode
	
	sei	;enable all interrupts	

	;Send synchronization sequence to receiver

	;*** Rear wheel speed reading ***

ADC_sta:;set up analog converter to read channel zero
	ldi	temp, 0
	out	ADMUX, temp

ch0_sta:sbis	ADCSR, ADSC	;Start conversion when ADSC bit is set
	rjmp	ch0_sta		;this bit is set by t1match interrupt

ch0_end:sbic	ADCSR, ADSC	;Wait for A to D done by checking is ADSC if cleared
	rjmp	ch0_end		;this bit is cleared by the AtoD hardware
	
	GET_OPCODE

	lsr	AnaLo
	lsr	AnaLo
	lsr	AnaLo

	mov	opcode, AnaLo
	
	;*** Front wheel direction reading ***

ch1_sta:ldi	temp, 4		;switch to channel 4
	out	ADMUX, temp
	sbi	ADCSR, ADSC	;Start A to D conversion on Ch1
		
ch1_end:sbic	ADCSR, ADSC	;Wait for A to D done by checking if ADSC is cleared
	rjmp	ch1_end		;this bit is cleared by the AtoD hardware

	GET_OPCODE

	andi	AnaLo, 0b11100000	;only need top 3 bits of direction
	or	opcode, AnaLo	
	
	ldi	temp, init_code
	clr	sendcode

send_init:
	out	UDR, temp
	
	tst	sendcode
	breq	send_init

	mov	temp, opcode
	com	temp
	out	PORTB, temp
	clr	sendcode

send_op:out	UDR, opcode
	
	tst	sendcode
	breq	send_op
	rjmp	ADC_sta
	
;**** timer 1 compare A match 1/sec
t1match:in	save, SREG
	ser	sendcode
	sbi	ADCSR, ADSC	;start ADC conversion
	out	SREG, save
	reti