$nolist 
r0     equ     0 
r1     equ     1 
r2     equ     2 
r3     equ     3  

orig    macro   addr         
cseg at 8000h 
base    equ     $         
cseg at 8000h+addr 
LED     equ     base+4000h         
endm  

ldx     macro   ra, rb, disp  ; rb can only be r2 or r3
        dcb     00h + (rb MOD 2) SHL 3 + (ra SHL 4) + (disp AND 07h)         
        endm

stx     macro   ra, rb, disp
         dcb     40h + (rb MOD 2) SHL 3 + (ra SHL 4) + (disp AND 07h)
         endm

addix   macro   ra, immed
         dcb     80h + (ra SHL 4) + (immed AND 0fh)
         endm

addx    macro   ra, rb
         dcb     0c0h + (ra SHL 4) + (rb SHL 2)
         endm

nandx   macro   ra, rb
         dcb     0c1h + (ra SHL 4) + (rb SHL 2)
         endm

sllx    macro   ra
         dcb     0c2h + (ra SHL 4)
          endm

notx    macro   ra
         dcb     0c6h + (ra SHL 4)
         endm

clrx    macro   ra
         dcb     0cah + (ra SHL 4)
          endm

jalx    macro
           dcb     0deh
         endm

skipnx  macro 
          dcb     0eeh
         endm

skipzx  macro
          dcb     0feh
         endm

brx     macro   label
         dcb     0c3h + ( ((label-$) AND 0fh) SHL 2)
         endm 

$list
$gen
 
 ; begin assembly lang test program 
	orig 0
 	clrx r2	
 	clrx r3
 	clrx r1		;clr increment reg
 	addix r1, 1	;set up r3 increment
 	addix r3,0fh 	;preset r3 0F
 	sllx r3		;preset r3 to F0
 	sllx r3
 	sllx r3
 	sllx r3
 	addix r3, 0eh	;preset r3 to FE
 	addx r2,r3	;pointer for storage for later	
 loop:	addx r3,r1	;increment r3
 	skipzx		;skip next inst if zero
 	brx loop	;junp back if not zero
 
 ; now test some other insts
 	addix r3,1
 	notx  r3
 	stx   r3,r2,0;store r3
 	clrx  r3
 	ldx   r3,r2,0;retrive r3
 
 hlt: 	brx hlt
 
 	end