Cornell University Elect Eng 475 Microprocessor Architectures

This is the home page for EE 475 which deals with computer architecture at the level of Computer Systems Design and Architecture by Vincent P. Heuring and Harry F. Jordan. EE 475 was taught in 1998 by Bruce Land. Bruce is also a staff member in Neurobiology and Behavior.

Contents

• Class overview and policy Read this immediately!
• Class Schedule & office hours
• Reading Assignments
• Course summary
• Homework
• Labs
• VHDL Tutorial
• Useful links

Staff

• Bruce Land,
  246 Mudd Hall, x4-4346, BRL4@cornell.edu
  

Lecture plans

Useful Links

• References for lab material
  • Xilinx homepage
  • Xilinx appnotes
  • XESS homepage
  • Synopsys homepage
  • XS40 Development Board
  • XC4010XL Data Sheet
  • FPGA pinout on the Xess board
    Note: This is NOT documented on the Xess schematic!
• Resources and VHDL designs
  • VHDL intro from EE3651 at Col Univ Denver
  • VHDL Reference Manual
  • Digital design by the author of the above link.
  • FPGAs on WWW
  • RISC Microprocessors In FPGAs
  • Brown EN164
  • 16-bit pipelined architecture on a Xilinx 4006
  • MIT beta processor.
  • U. of Aizu
  • VHDL floating point
  • VHDL models
  • VHDL cpu design at Northeastern Univ.
  • VHDL tools
  • VHDL models
  • VHDL and FPGAs
  • VHDL Sparc design
  • HOKIE processor from Virginia Tech
  • DSP on FPGA from Kansas
  • Intro to RISC Technology
• Microprocessor debugging environment
  • xsdebug.c The C source code for the DOS debugger
  • shell.vhd The VHDL side of the interface
  • shell.ucf The pin assignment of the debugging system
  • For an example of its use, see the following design.
• Ken's microprocessor design
  • cpu.vhd The VHDL design of the CPU
  • cpu.ucf The pin assignment of the CPU
  • counter.asm A demonstration assembly language program
  • asm.asm The macro file so ASM96 can assemble this language
• Bruce's microprocessor design #1
  8-bit, load/store, based on MICA design.
  • Instruction set. (from Notre Dame)
  • Initial Datapath. (from Notre Dame)
  • Datapath implemented.
  • Timing.
  • VHDL source.
  • Assembler
• Bruce's microprocessor design #2
  8-bit, load/store, pipelined, based on AIZUP design.
  • Original Design. (from U. Aizu)
  • Datapath implemented.
  • VHDL for serial processor.
  • VHDL for overlapped fetch/execute.
  • VHDL for 4-stage pipeline.
  • Assembler + test-pgm for pipeline design
• SRC assembler and simulator
  • Assembler and Simulator compiled for Win32 systems: This is a command prompt version of the SRC assembler and simulator that will only run under Windows 95, Windows NT, or a Windows 3.1 system with Win32 installed.
• Commercial microprocessor info
  • HP VLSI Technology Center.
  • Intel Merced processor.

Copyright 1998 Cornell University