SYSTEM bigNios
{
System_Wizard_Version = "6.00";
System_Wizard_Build = "202";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONEII";
clock_freq = "50000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "0";
hardcopy_compatible = "0";
board_class = "";
CLOCKS
{
CLOCK clk
{
frequency = "50000000";
source = "External";
display_name = "clk";
Is_Clock_Source = "0";
}
}
hdl_language = "verilog";
device_family_id = "CYCLONEII";
view_master_columns = "1";
view_master_priorities = "0";
name_column_width = "237";
desc_column_width = "238";
bustype_column_width = "0";
base_column_width = "75";
clock_column_width = "80";
end_column_width = "75";
view_frame_window = "128:128:1024:768";
do_log_history = "0";
}
MODULE cpu_0
{
class = "altera_nios2";
class_version = "6.0";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.v, __PROJECT_DIRECTORY__/cpu_0_mult_cell.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu_0.v";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT i_address
{
Is_Enabled = "1";
direction = "output";
type = "address";
width = "24";
}
PORT i_read
{
Is_Enabled = "1";
direction = "output";
type = "read";
width = "1";
}
PORT i_readdata
{
Is_Enabled = "1";
direction = "input";
type = "readdata";
width = "32";
}
PORT i_readdatavalid
{
Is_Enabled = "1";
direction = "input";
type = "readdatavalid";
width = "1";
}
PORT i_waitrequest
{
Is_Enabled = "1";
direction = "input";
type = "waitrequest";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
Is_Big_Endian = "0";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Linewrap_Bursts = "";
Interleave_Bursts = "";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT d_address
{
Is_Enabled = "1";
direction = "output";
type = "address";
width = "24";
}
PORT d_byteenable
{
Is_Enabled = "1";
direction = "output";
type = "byteenable";
width = "4";
}
PORT d_irq
{
Is_Enabled = "1";
direction = "input";
type = "irq";
width = "32";
}
PORT d_read
{
Is_Enabled = "1";
direction = "output";
type = "read";
width = "1";
}
PORT d_readdata
{
Is_Enabled = "1";
direction = "input";
type = "readdata";
width = "32";
}
PORT d_waitrequest
{
Is_Enabled = "1";
direction = "input";
type = "waitrequest";
width = "1";
}
PORT d_write
{
Is_Enabled = "1";
direction = "output";
type = "write";
width = "1";
}
PORT d_writedata
{
Is_Enabled = "1";
direction = "output";
type = "writedata";
width = "32";
}
PORT jtag_debug_module_debugaccess_to_roms
{
Is_Enabled = "1";
direction = "output";
type = "debugaccess";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
Is_Big_Endian = "0";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
}
}
MASTER data_master2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
Is_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
SLAVE jtag_debug_module
{
PORT_WIRING
{
PORT jtag_debug_module_address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "9";
}
PORT jtag_debug_module_begintransfer
{
Is_Enabled = "1";
direction = "input";
type = "begintransfer";
width = "1";
}
PORT jtag_debug_module_byteenable
{
Is_Enabled = "1";
direction = "input";
type = "byteenable";
width = "4";
}
PORT jtag_debug_module_clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT jtag_debug_module_debugaccess
{
Is_Enabled = "1";
direction = "input";
type = "debugaccess";
width = "1";
}
PORT jtag_debug_module_readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "32";
}
PORT jtag_debug_module_reset
{
Is_Enabled = "1";
direction = "input";
type = "reset";
width = "1";
}
PORT jtag_debug_module_resetrequest
{
Is_Enabled = "1";
direction = "output";
type = "resetrequest";
width = "1";
}
PORT jtag_debug_module_select
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT jtag_debug_module_write
{
Is_Enabled = "1";
direction = "input";
type = "write";
width = "1";
}
PORT jtag_debug_module_writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "32";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Read_Wait_States = "1";
Write_Wait_States = "1";
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Address_Width = "9";
Accepts_Internal_Connections = "1";
Requires_Internal_Connections = "instruction_master,data_master";
Accepts_External_Connections = "0";
Is_Enabled = "1";
Address_Alignment = "dynamic";
Base_Address = "0x00000000";
Is_Memory_Device = "1";
Is_Readable = "1";
Is_Writeable = "1";
Is_Printable_Device = "0";
Is_Big_Endian = "0";
Uses_Tri_State_Data_Bus = "0";
Has_IRQ = "0";
JTAG_Hub_Base_Id = "1118278";
JTAG_Hub_Instance_Id = "0";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
PORT_WIRING
{
PORT jtag_debug_trigout
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "0";
}
PORT clkx2
{
width = "1";
direction = "input";
Is_Enabled = "0";
visible = "0";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
asp_debug = "0";
asp_core_debug = "0";
CPU_Architecture = "nios2";
do_generate = "1";
cpu_selection = "s";
CPU_Implementation = "small";
gui_include_tightly_coupled_instruction_masters = "0";
gui_num_tightly_coupled_instruction_masters = "1";
gui_omit_avalon_data_master = "0";
gui_include_tightly_coupled_data_masters = "0";
gui_num_tightly_coupled_data_masters = "1";
num_tightly_coupled_instruction_masters = "0";
num_tightly_coupled_data_masters = "0";
cache_has_dcache = "0";
cache_has_icache = "1";
cache_dcache_size = "2048";
cache_icache_size = "4096";
cache_dcache_line_size = "4";
cache_icache_line_size = "32";
cache_dcache_bursts = "0";
cache_icache_burst_type = "none";
cache_dcache_ram_block_type = "AUTO";
cache_icache_ram_block_type = "AUTO";
include_debug = "0";
include_trace = "0";
include_oci = "1";
include_third_party_debug_port = "0";
debug_level = "2";
oci_offchip_trace = "0";
oci_onchip_trace = "0";
oci_data_trace = "0";
oci_trace_addr_width = "7";
oci_num_xbrk = "0";
oci_num_dbrk = "0";
oci_dbrk_trace = "0";
oci_dbrk_pairs = "0";
oci_num_pm = "0";
oci_pm_width = "40";
oci_debugreq_signals = "0";
oci_trigger_arming = "1";
oci_embedded_pll = "1";
hardware_multiply_present = "1";
hardware_divide_present = "0";
gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
hardware_multiply_uses_les = "0";
hardware_multiply_omits_msw = "1";
hardware_multiply_impl = "embedded_mul";
gui_hardware_divide_setting = "0";
cpu_reset = "0";
export_pcb = "0";
big_endian = "0";
reset_slave = "sdram_0/s1";
reset_offset = "0x00000000";
exc_slave = "sdram_0/s1";
exc_offset = "0x00000020";
break_slave = "cpu_0/jtag_debug_module";
break_offset = "0x00000020";
break_slave_override = "";
break_offset_override = "0x20";
legacy_sdk_support = "0";
altera_show_unreleased_features = "0";
altera_show_unpublished_features = "0";
altera_internal_test = "0";
alt_log_port_base = "";
alt_log_port_type = "";
full_waveform_signals = "0";
gui_illegal_instructions_trap = "0";
illegal_instructions_trap = "0";
gui_illegal_memory_access_detection = "0";
illegal_memory_access_detection = "0";
gui_branch_prediction_type = "Automatic";
branch_prediction_type = "Static";
bht_ptr_sz = "8";
bht_index_pc_only = "0";
shift_rot_impl = "fast_le_shift";
gui_mmu_present = "0";
mmu_present = "0";
process_id_num_bits = "10";
dtlb_ptr_sz = "7";
dtlb_num_ways = "4";
udtlb_num_entries = "6";
itlb_ptr_sz = "7";
itlb_num_ways = "4";
uitlb_num_entries = "4";
fast_tlb_miss_exc_slave = "";
fast_tlb_miss_exc_offset = "0x0";
cache_omit_dcache = "0";
cache_omit_icache = "0";
omit_instruction_master = "0";
omit_data_master = "0";
performance_counters_present = "0";
performance_counters_width = "32";
ras_ptr_sz = "4";
jtb_ptr_sz = "5";
ibuf_ptr_sz = "4";
always_encrypt = "1";
debug_simgen = "0";
activate_model_checker = "0";
activate_monitors = "1";
activate_test_end_checker = "0";
activate_trace = "1";
clear_x_bits_ld_non_bypass = "1";
bit_31_bypass_dcache = "1";
always_bypass_dcache = "0";
hdl_sim_caches_cleared = "1";
consistent_synthesis = "0";
hbreak_test = "0";
allow_full_address_range = "0";
allow_legacy_sdk = "0";
iss_trace_on = "0";
iss_trace_warning = "1";
iss_trace_info = "1";
iss_trace_disassembly = "0";
iss_trace_registers = "0";
iss_trace_instr_count = "0";
iss_software_debug = "0";
iss_software_debug_port = "9996";
iss_memory_dump_start = "";
iss_memory_dump_end = "";
Boot_Copier = "boot_loader_cfi.srec";
Boot_Copier_EPCS = "boot_loader_epcs.srec";
Boot_Copier_EPCS_Stratix_II = "boot_loader_epcs_stratix_ii.srec";
CONSTANTS
{
CONSTANT __nios_catch_irqs__
{
value = "1";
comment = "Include panic handler for all irqs (needs uart)";
}
CONSTANT __nios_use_constructors__
{
value = "1";
comment = "Call c++ static constructors";
}
CONSTANT __nios_use_small_printf__
{
value = "1";
comment = "Smaller non-ANSI printf, with no floating point";
}
CONSTANT nasys_has_icache
{
value = "1";
comment = "True if instruction cache present";
}
CONSTANT nasys_icache_size
{
value = "4096";
comment = "Size in bytes of instruction cache";
}
CONSTANT nasys_icache_line_size
{
value = "32";
comment = "Size in bytes of each icache line";
}
CONSTANT nasys_icache_line_size_log2
{
value = "5";
comment = "Log2 size in bytes of each icache line";
}
CONSTANT nasys_has_dcache
{
value = "0";
comment = "True if instruction cache present";
}
CONSTANT nasys_dcache_size
{
value = "2048";
comment = "Size in bytes of data cache";
}
CONSTANT nasys_dcache_line_size
{
value = "4";
comment = "Size in bytes of each dcache line";
}
CONSTANT nasys_dcache_line_size_log2
{
value = "2";
comment = "Log2 size in bytes of each dcache line";
}
}
license_status = "ocp";
germs_monitor_id = "";
cpuid_sz = "1";
cpuid_value = "0";
}
SYSTEM_BUILDER_INFO
{
Parameters_Signature = "";
Is_CPU = "1";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,CYCLONE,CYCLONEII";
Default_Module_Name = "cpu";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
MESSAGES
{
}
Is_Collapsed = "0";
Settings_Summary = "Nios II/s
4-Kbyte Instruction Cache
JTAG Debug Module
";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "6.0";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL aaa
{
format = "Logic";
name = "i_readdata";
radix = "hexadecimal";
}
SIGNAL aab
{
format = "Logic";
name = "i_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aac
{
format = "Logic";
name = "i_waitrequest";
radix = "hexadecimal";
}
SIGNAL aad
{
format = "Logic";
name = "i_address";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "i_read";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aag
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "d_readdata";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "d_waitrequest";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "d_irq";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "d_address";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Logic";
name = "d_byteenable";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "d_read";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "d_write";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Logic";
name = "d_writedata";
radix = "hexadecimal";
}
SIGNAL aap
{
format = "Divider";
name = "base pipeline";
radix = "";
}
SIGNAL aaq
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "M_stall";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL aau
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL aav
{
format = "Logic";
name = "D_pcb";
radix = "hexadecimal";
}
SIGNAL aaw
{
format = "Logic";
name = "E_pcb";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "M_pcb";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "W_pcb";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL aba
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL abb
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL abc
{
format = "Logic";
name = "M_vinst";
radix = "ascii";
}
SIGNAL abd
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL abe
{
format = "Logic";
name = "F_inst_ram_hit";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "F_issue";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Logic";
name = "F_kill";
radix = "hexadecimal";
}
SIGNAL abh
{
format = "Logic";
name = "D_kill";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "D_refetch";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "D_issue";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL abl
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL abm
{
format = "Logic";
name = "M_valid";
radix = "hexadecimal";
}
SIGNAL abn
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abo
{
format = "Logic";
name = "W_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abp
{
format = "Logic";
name = "W_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abq
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abr
{
format = "Logic";
name = "F_en";
radix = "hexadecimal";
}
SIGNAL abs
{
format = "Logic";
name = "D_en";
radix = "hexadecimal";
}
SIGNAL abt
{
format = "Logic";
name = "E_en";
radix = "hexadecimal";
}
SIGNAL abu
{
format = "Logic";
name = "M_en";
radix = "hexadecimal";
}
SIGNAL abv
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abw
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abx
{
format = "Logic";
name = "E_iw";
radix = "hexadecimal";
}
SIGNAL aby
{
format = "Logic";
name = "E_valid_prior_to_hbreak";
radix = "hexadecimal";
}
SIGNAL abz
{
format = "Logic";
name = "M_pipe_flush_nxt";
radix = "hexadecimal";
}
SIGNAL aca
{
format = "Logic";
name = "M_pipe_flush_baddr_nxt";
radix = "hexadecimal";
}
SIGNAL acb
{
format = "Logic";
name = "M_status_reg_pie";
radix = "hexadecimal";
}
SIGNAL acc
{
format = "Logic";
name = "M_ienable_reg";
radix = "hexadecimal";
}
SIGNAL acd
{
format = "Logic";
name = "intr_req";
radix = "hexadecimal";
}
}
}
}
MODULE sdram_0
{
class = "altera_avalon_new_sdram_controller";
class_version = "6.01";
iss_model_name = "altera_memory";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Alignment = "dynamic";
Has_IRQ = "0";
Maximum_Pending_Read_Transactions = "7";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
Is_Memory_Device = "1";
Address_Width = "22";
Data_Width = "16";
Simulation_Num_Lanes = "1";
MASTERED_BY cpu_0/instruction_master
{
priority = "1";
}
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Base_Address = "0x00800000";
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
PORT_WIRING
{
PORT zs_addr
{
direction = "output";
width = "12";
Is_Enabled = "1";
}
PORT zs_ba
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_cas_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cke
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_cs_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_dq
{
direction = "inout";
width = "16";
Is_Enabled = "1";
}
PORT zs_dqm
{
direction = "output";
width = "2";
Is_Enabled = "1";
}
PORT zs_ras_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT zs_we_n
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT az_addr
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "22";
}
PORT az_be_n
{
Is_Enabled = "1";
direction = "input";
type = "byteenable_n";
width = "2";
}
PORT az_cs
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT az_data
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
PORT az_rd_n
{
Is_Enabled = "1";
direction = "input";
type = "read_n";
width = "1";
}
PORT az_wr_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT za_data
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT za_valid
{
Is_Enabled = "1";
direction = "output";
type = "readdatavalid";
width = "1";
}
PORT za_waitrequest
{
Is_Enabled = "1";
direction = "output";
type = "waitrequest";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Default_Module_Name = "sdram";
Disable_Simulation_Port_Wiring = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "4194304 x 16
Memory size: 8 MBytes
64 MBits
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
register_data_in = "1";
sim_model_base = "0";
sdram_data_width = "16";
sdram_addr_width = "12";
sdram_row_width = "12";
sdram_col_width = "8";
sdram_num_chipselects = "1";
sdram_num_banks = "4";
refresh_period = "15.625";
powerup_delay = "100";
cas_latency = "3";
t_rfc = "70";
t_rp = "20";
t_mrd = "3";
t_rcd = "20";
t_ac = "5.5";
t_wr = "14";
init_refresh_commands = "2";
init_nop_delay = "0";
shared_data = "0";
starvation_indicator = "0";
tristate_bridge_slave = "";
is_initialized = "1";
sdram_bank_width = "2";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL a
{
name = "az_addr";
radix = "hexadecimal";
}
SIGNAL b
{
name = "az_be_n";
radix = "hexadecimal";
}
SIGNAL c
{
name = "az_cs";
}
SIGNAL d
{
name = "az_data";
radix = "hexadecimal";
}
SIGNAL e
{
name = "az_rd_n";
}
SIGNAL f
{
name = "az_wr_n";
}
SIGNAL g
{
name = "clk";
}
SIGNAL h
{
name = "za_data";
radix = "hexadecimal";
}
SIGNAL i
{
name = "za_valid";
}
SIGNAL j
{
name = "za_waitrequest";
}
SIGNAL k
{
name = "za_cannotrefresh";
suppress = "1";
}
SIGNAL l
{
name = "CODE";
radix = "ascii";
}
SIGNAL m
{
name = "zs_addr";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL n
{
name = "zs_ba";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL o
{
name = "zs_cs_n";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL p
{
name = "zs_ras_n";
suppress = "0";
}
SIGNAL q
{
name = "zs_cas_n";
suppress = "0";
}
SIGNAL r
{
name = "zs_we_n";
suppress = "0";
}
SIGNAL s
{
name = "zs_dq";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL t
{
name = "zs_dqm";
radix = "hexadecimal";
suppress = "0";
}
SIGNAL u
{
name = "zt_addr";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL v
{
name = "zt_ba";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL w
{
name = "zt_oe";
suppress = "1";
}
SIGNAL x
{
name = "zt_cke";
suppress = "1";
}
SIGNAL y
{
name = "zt_chipselect";
suppress = "1";
}
SIGNAL z0
{
name = "zt_lock_n";
suppress = "1";
}
SIGNAL z1
{
name = "zt_ras_n";
suppress = "1";
}
SIGNAL z2
{
name = "zt_cas_n";
suppress = "1";
}
SIGNAL z3
{
name = "zt_we_n";
suppress = "1";
}
SIGNAL z4
{
name = "zt_cs_n";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z5
{
name = "zt_dqm";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z6
{
name = "zt_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z7
{
name = "tz_data";
radix = "hexadecimal";
suppress = "1";
}
SIGNAL z8
{
name = "tz_waitrequest";
suppress = "1";
}
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram_0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE lcd
{
class = "altera_avalon_lcd_16207";
class_version = "6.01";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lcd.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT LCD_data
{
direction = "inout";
width = "8";
Is_Enabled = "1";
}
PORT LCD_E
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT LCD_RS
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT LCD_RW
{
direction = "output";
width = "1";
Is_Enabled = "1";
}
}
SLAVE control_slave
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT begintransfer
{
Is_Enabled = "1";
direction = "input";
type = "begintransfer";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT read
{
Is_Enabled = "1";
direction = "input";
type = "read";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "8";
}
PORT write
{
Is_Enabled = "1";
direction = "input";
type = "write";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "8";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Is_Printable_Device = "1";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x00000800";
Address_Alignment = "native";
Read_Wait_States = "250ns";
Write_Wait_States = "250ns";
Setup_Time = "250ns";
Hold_Time = "250ns";
Read_Latency = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Top_Level_Ports_Are_Enumerated = "1";
View
{
Is_Collapsed = "1";
MESSAGES
{
}
}
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
}
}
MODULE jtag_uart_0
{
class = "altera_avalon_jtag_uart";
class_version = "6.01";
iss_model_name = "altera_avalon_jtag_uart";
SLAVE avalon_jtag_slave
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "1";
Address_Alignment = "native";
Address_Width = "1";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "peripheral_controlled";
Write_Wait_States = "peripheral_controlled";
JTAG_Hub_Base_Id = "0x04006E";
JTAG_Hub_Instance_Id = "0";
Connection_Limit = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "0";
}
Base_Address = "0x00000810";
Address_Group = "0";
}
PORT_WIRING
{
PORT clk
{
type = "clk";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT rst_n
{
type = "reset_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_chipselect
{
type = "chipselect";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_address
{
type = "address";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_read_n
{
type = "read_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_readdata
{
type = "readdata";
direction = "output";
width = "32";
Is_Enabled = "1";
}
PORT av_write_n
{
type = "write_n";
direction = "input";
width = "1";
Is_Enabled = "1";
}
PORT av_writedata
{
type = "writedata";
direction = "input";
width = "32";
Is_Enabled = "1";
}
PORT av_waitrequest
{
type = "waitrequest";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT av_irq
{
type = "irq";
direction = "output";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
Is_Enabled = "1";
direction = "output";
type = "dataavailable";
width = "1";
}
PORT readyfordata
{
Is_Enabled = "1";
direction = "output";
type = "readyfordata";
width = "1";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Iss_Launch_Telnet = "0";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "
Write Depth: 64; Write IRQ Threshold: 8
Read Depth: 64; Read IRQ Threshold: 8";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
write_depth = "64";
read_depth = "64";
write_threshold = "8";
read_threshold = "8";
read_char_stream = "";
showascii = "1";
read_le = "0";
write_le = "0";
altera_show_unreleased_jtag_uart_features = "0";
}
SIMULATION
{
Fix_Me_Up = "";
DISPLAY
{
SIGNAL av_chipselect
{
name = "av_chipselect";
}
SIGNAL av_address
{
name = "av_address";
radix = "hexadecimal";
}
SIGNAL av_read_n
{
name = "av_read_n";
}
SIGNAL av_readdata
{
name = "av_readdata";
radix = "hexadecimal";
}
SIGNAL av_write_n
{
name = "av_write_n";
}
SIGNAL av_writedata
{
name = "av_writedata";
radix = "hexadecimal";
}
SIGNAL av_waitrequest
{
name = "av_waitrequest";
}
SIGNAL av_irq
{
name = "av_irq";
}
SIGNAL dataavailable
{
name = "dataavailable";
}
SIGNAL readyfordata
{
name = "readyfordata";
}
}
INTERACTIVE_IN drive
{
enable = "0";
file = "_input_data_stream.dat";
mutex = "_input_data_mutex.dat";
log = "_in.log";
rate = "100";
signals = "temp,list";
exe = "nios2-terminal";
}
INTERACTIVE_OUT log
{
enable = "1";
exe = "perl -- atail-f.pl";
file = "_output_stream.dat";
radix = "ascii";
signals = "temp,list";
}
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
MODULE Out0
{
class = "altera_avalon_pio";
class_version = "6.01";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Out0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "32";
}
PORT out_port
{
direction = "output";
Is_Enabled = "1";
width = "32";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "32";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "32";
Base_Address = "0x00000820";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Is_Readable = "0";
Is_Writable = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 32-bit PIO using
output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE Out1
{
class = "altera_avalon_pio";
class_version = "6.01";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Out1.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "0";
width = "32";
}
PORT out_port
{
direction = "output";
Is_Enabled = "1";
width = "32";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "32";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "32";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "32";
Base_Address = "0x00000830";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Is_Readable = "0";
Is_Writable = "1";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 32-bit PIO using
output pins";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "1";
has_in = "0";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE In0
{
class = "altera_avalon_pio";
class_version = "6.01";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/In0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "1";
width = "32";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "32";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "32";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "32";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "32";
Base_Address = "0x00000840";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Is_Readable = "1";
Is_Writable = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 32-bit PIO using
input pins with edge type NONE and interrupt source NONE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE In1_8bit
{
class = "altera_avalon_pio";
class_version = "6.01";
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/In1_8bit.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
PORT in_port
{
direction = "input";
Is_Enabled = "1";
width = "8";
}
PORT out_port
{
direction = "output";
Is_Enabled = "0";
width = "8";
}
PORT bidir_port
{
direction = "inout";
Is_Enabled = "0";
width = "8";
}
}
SLAVE s1
{
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "2";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "8";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Has_IRQ = "0";
Address_Width = "2";
Data_Width = "8";
Base_Address = "0x00000850";
Address_Alignment = "native";
Read_Wait_States = "1";
Write_Wait_States = "0";
Is_Readable = "1";
Is_Writable = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
Address_Group = "0";
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "NC";
}
}
}
SYSTEM_BUILDER_INFO
{
Date_Modified = "";
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Wire_Test_Bench_Values = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = " 8-bit PIO using
input pins with edge type NONE and interrupt source NONE
";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
Do_Test_Bench_Wiring = "0";
Driven_Sim_Value = "0x0000";
has_tri = "0";
has_out = "0";
has_in = "1";
capture = "0";
edge_type = "NONE";
irq_type = "NONE";
}
}
MODULE timer_0
{
class = "altera_avalon_timer";
class_version = "6.01";
iss_model_name = "altera_avalon_timer";
SLAVE s1
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "native";
Address_Width = "3";
Data_Width = "16";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "0";
MASTERED_BY cpu_0/data_master
{
priority = "1";
}
IRQ_MASTER cpu_0/data_master
{
IRQ_Number = "1";
}
Base_Address = "0x00000860";
Address_Group = "0";
}
PORT_WIRING
{
PORT address
{
Is_Enabled = "1";
direction = "input";
type = "address";
width = "3";
}
PORT chipselect
{
Is_Enabled = "1";
direction = "input";
type = "chipselect";
width = "1";
}
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT irq
{
Is_Enabled = "1";
direction = "output";
type = "irq";
width = "1";
}
PORT readdata
{
Is_Enabled = "1";
direction = "output";
type = "readdata";
width = "16";
}
PORT reset_n
{
Is_Enabled = "1";
direction = "input";
type = "reset_n";
width = "1";
}
PORT write_n
{
Is_Enabled = "1";
direction = "input";
type = "write_n";
width = "1";
}
PORT writedata
{
Is_Enabled = "1";
direction = "input";
type = "writedata";
width = "16";
}
}
}
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
Is_Enabled = "1";
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
View
{
Settings_Summary = "Timer with 1 ms timeout period.";
MESSAGES
{
}
Is_Collapsed = "1";
}
}
WIZARD_SCRIPT_ARGUMENTS
{
always_run = "0";
fixed_period = "0";
snapshot = "1";
period = "1";
period_units = "ms";
reset_output = "0";
timeout_pulse_output = "0";
mult = "0.001";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/timer_0.v";
Synthesis_Only_Files = "";
}
PORT_WIRING
{
}
}
}