module cnt(out,cas,c1,c2,c3,c4,c5,c6, clk, rst); 
   input wire c1,c2,c3,c4,c5,c6; 
   input wire clk; 
   output reg [6:0] out; 
   output reg         cas; 	// this is the output cn (n=integer) 
   input wire         rst; 
   wire         c; 

   assign c = c1&c2&c3&c4&c5&c6; 

   always@(posedge clk or posedge rst) 
     begin 
    if(rst) 
      begin 
         out<=7'b0;    	// counter output 
         cas<=1'b0; 
      end 
    else 
      if(c) 
        begin 
           if(out==7'd68) 
    	 begin 
    	    cas<=1'b1; 	// prime the cascaded units 
    	    out<=out+7'd1; 
    	 end 
           else if(out==7'd69) 
    	 begin 
    	    out<=7'd1;	//wrap around to 7'b1 not 7'b0. skipping 0. 
    	    cas<=1'b0; 
    	 end 
           else 
    	 begin 
    	    out<=out+7'd1; 
    	 end 
        end //  if (c)
     end //  always@ (posedge clk or posedge rst)
endmodule //  cnt


//head counter--very first one in the chain (lsb) 
//counts by +10 
module cnt10(out,cas,clk,rst,preset); 
   input wire clk;    	// not an actual clk, toggle this to count up 
   input wire [6:0] preset; 
   output reg [6:0] out; 
   output reg         cas; 	// this is the output cn (n=integer) 
   input wire         rst; 
   reg [6:0]         sum; 

   always@(posedge clk or posedge rst) 
     begin 
    if(rst) 
      begin 
         out<=preset; 
         cas<=1'b0; 
      end 
    else 
        begin 
           if(out>7'd59) 	// adding 10 will overflow 
    	 begin 
    	    cas<=1'b0; 	 
    	    out<= out-7'd60+7'd1; //  plus 10, overflow, wrap around and skipping 0. effectively +11
    	 end 
           else 
    	 begin 
    	    out<=out+7'd10; //  no need to wrap around, just count up by 10
    	    if(out+7'd20>7'd69) //  predict the overflow in advance so we can assert the cas signal correctly
    	      begin 
    		 cas<=1'b1;	    //  prime the next unit
    	      end 
    	 end 
        end 
     end //  always@ (posedge clk or posedge rst)
endmodule //  cnt


module count(b1,b2,b3,b4,b5,b6,b7,c_clk,rst,preset); 
   output wire [6:0] b1,b2,b3,b4,b5,b6,b7; 
   wire          c1,c2,c3,c4,c5,c6,c7; 
   input wire [6:0]  preset; 
   input wire          c_clk, rst; 
   cnt10 cnt1(b1,c1,c_clk,rst,preset); //  +10 counter
   cnt cnt2(b2,c2,c1,1'b1,1'b1,1'b1,1'b1,1'b1,c_clk,rst); //  +1 counter
   cnt cnt3(b3,c3,c1,c2,1'b1,1'b1,1'b1,1'b1,c_clk,rst); 
   cnt cnt4(b4,c4,c1,c2,c3,1'b1,1'b1,1'b1,c_clk,rst); 
   cnt cnt5(b5,c5,c1,c2,c3,c4,1'b1,1'b1,c_clk,rst); 
   cnt cnt6(b6,c6,c1,c2,c3,c4,c5,1'b1,c_clk,rst); 
   cnt cnt7(b7,c7,c1,c2,c3,c4,c5,c6,c_clk,rst);
endmodule