//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module In0_s1_arbitrator (
                           // inputs:
                            In0_s1_readdata,
                            clk,
                            cpu_0_data_master_address_to_slave,
                            cpu_0_data_master_read,
                            cpu_0_data_master_write,
                            reset_n,

                           // outputs:
                            In0_s1_address,
                            In0_s1_readdata_from_sa,
                            In0_s1_reset_n,
                            cpu_0_data_master_granted_In0_s1,
                            cpu_0_data_master_qualified_request_In0_s1,
                            cpu_0_data_master_read_data_valid_In0_s1,
                            cpu_0_data_master_requests_In0_s1,
                            d1_In0_s1_end_xfer
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] In0_s1_address;
  output  [ 15: 0] In0_s1_readdata_from_sa;
  output           In0_s1_reset_n;
  output           cpu_0_data_master_granted_In0_s1;
  output           cpu_0_data_master_qualified_request_In0_s1;
  output           cpu_0_data_master_read_data_valid_In0_s1;
  output           cpu_0_data_master_requests_In0_s1;
  output           d1_In0_s1_end_xfer;
  input   [ 15: 0] In0_s1_readdata;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_write;
  input            reset_n;

  wire    [  1: 0] In0_s1_address;
  wire             In0_s1_allgrants;
  wire             In0_s1_allow_new_arb_cycle;
  wire             In0_s1_any_bursting_master_saved_grant;
  wire             In0_s1_any_continuerequest;
  wire             In0_s1_arb_counter_enable;
  reg     [  1: 0] In0_s1_arb_share_counter;
  wire    [  1: 0] In0_s1_arb_share_counter_next_value;
  wire    [  1: 0] In0_s1_arb_share_set_values;
  wire             In0_s1_beginbursttransfer_internal;
  wire             In0_s1_begins_xfer;
  wire             In0_s1_end_xfer;
  wire             In0_s1_firsttransfer;
  wire             In0_s1_grant_vector;
  wire             In0_s1_in_a_read_cycle;
  wire             In0_s1_in_a_write_cycle;
  wire             In0_s1_master_qreq_vector;
  wire             In0_s1_non_bursting_master_requests;
  wire    [ 15: 0] In0_s1_readdata_from_sa;
  wire             In0_s1_reset_n;
  reg              In0_s1_slavearbiterlockenable;
  wire             In0_s1_slavearbiterlockenable2;
  wire             In0_s1_waits_for_read;
  wire             In0_s1_waits_for_write;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_In0_s1;
  wire             cpu_0_data_master_qualified_request_In0_s1;
  wire             cpu_0_data_master_read_data_valid_In0_s1;
  wire             cpu_0_data_master_requests_In0_s1;
  wire             cpu_0_data_master_saved_grant_In0_s1;
  reg              d1_In0_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_In0_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_In0_s1_from_cpu_0_data_master;
  wire             wait_for_In0_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~In0_s1_end_xfer;
    end


  assign In0_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_In0_s1));
  //assign In0_s1_readdata_from_sa = In0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign In0_s1_readdata_from_sa = In0_s1_readdata;

  assign cpu_0_data_master_requests_In0_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h820) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
  //In0_s1_arb_share_counter set values, which is an e_mux
  assign In0_s1_arb_share_set_values = 1;

  //In0_s1_non_bursting_master_requests mux, which is an e_mux
  assign In0_s1_non_bursting_master_requests = cpu_0_data_master_requests_In0_s1;

  //In0_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign In0_s1_any_bursting_master_saved_grant = 0;

  //In0_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign In0_s1_arb_share_counter_next_value = In0_s1_firsttransfer ? (In0_s1_arb_share_set_values - 1) : |In0_s1_arb_share_counter ? (In0_s1_arb_share_counter - 1) : 0;

  //In0_s1_allgrants all slave grants, which is an e_mux
  assign In0_s1_allgrants = |In0_s1_grant_vector;

  //In0_s1_end_xfer assignment, which is an e_assign
  assign In0_s1_end_xfer = ~(In0_s1_waits_for_read | In0_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_In0_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_In0_s1 = In0_s1_end_xfer & (~In0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //In0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign In0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_In0_s1 & In0_s1_allgrants) | (end_xfer_arb_share_counter_term_In0_s1 & ~In0_s1_non_bursting_master_requests);

  //In0_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          In0_s1_arb_share_counter <= 0;
      else if (In0_s1_arb_counter_enable)
          In0_s1_arb_share_counter <= In0_s1_arb_share_counter_next_value;
    end


  //In0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          In0_s1_slavearbiterlockenable <= 0;
      else if ((|In0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_In0_s1) | (end_xfer_arb_share_counter_term_In0_s1 & ~In0_s1_non_bursting_master_requests))
          In0_s1_slavearbiterlockenable <= |In0_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master In0/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = In0_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //In0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign In0_s1_slavearbiterlockenable2 = |In0_s1_arb_share_counter_next_value;

  //cpu_0/data_master In0/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = In0_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //In0_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign In0_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_In0_s1 = cpu_0_data_master_requests_In0_s1;
  //master is always granted when requested
  assign cpu_0_data_master_granted_In0_s1 = cpu_0_data_master_qualified_request_In0_s1;

  //cpu_0/data_master saved-grant In0/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_In0_s1 = cpu_0_data_master_requests_In0_s1;

  //allow new arb cycle for In0/s1, which is an e_assign
  assign In0_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign In0_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign In0_s1_master_qreq_vector = 1;

  //In0_s1_reset_n assignment, which is an e_assign
  assign In0_s1_reset_n = reset_n;

  //In0_s1_firsttransfer first transaction, which is an e_assign
  assign In0_s1_firsttransfer = ~(In0_s1_slavearbiterlockenable & In0_s1_any_continuerequest);

  //In0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign In0_s1_beginbursttransfer_internal = In0_s1_begins_xfer;

  assign shifted_address_to_In0_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //In0_s1_address mux, which is an e_mux
  assign In0_s1_address = shifted_address_to_In0_s1_from_cpu_0_data_master >> 2;

  //d1_In0_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_In0_s1_end_xfer <= 1;
      else if (1)
          d1_In0_s1_end_xfer <= In0_s1_end_xfer;
    end


  //In0_s1_waits_for_read in a cycle, which is an e_mux
  assign In0_s1_waits_for_read = In0_s1_in_a_read_cycle & In0_s1_begins_xfer;

  //In0_s1_in_a_read_cycle assignment, which is an e_assign
  assign In0_s1_in_a_read_cycle = cpu_0_data_master_granted_In0_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = In0_s1_in_a_read_cycle;

  //In0_s1_waits_for_write in a cycle, which is an e_mux
  assign In0_s1_waits_for_write = In0_s1_in_a_write_cycle & 0;

  //In0_s1_in_a_write_cycle assignment, which is an e_assign
  assign In0_s1_in_a_write_cycle = cpu_0_data_master_granted_In0_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = In0_s1_in_a_write_cycle;

  assign wait_for_In0_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module In1_s1_arbitrator (
                           // inputs:
                            In1_s1_readdata,
                            clk,
                            cpu_0_data_master_address_to_slave,
                            cpu_0_data_master_read,
                            cpu_0_data_master_write,
                            reset_n,

                           // outputs:
                            In1_s1_address,
                            In1_s1_readdata_from_sa,
                            In1_s1_reset_n,
                            cpu_0_data_master_granted_In1_s1,
                            cpu_0_data_master_qualified_request_In1_s1,
                            cpu_0_data_master_read_data_valid_In1_s1,
                            cpu_0_data_master_requests_In1_s1,
                            d1_In1_s1_end_xfer
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] In1_s1_address;
  output  [ 15: 0] In1_s1_readdata_from_sa;
  output           In1_s1_reset_n;
  output           cpu_0_data_master_granted_In1_s1;
  output           cpu_0_data_master_qualified_request_In1_s1;
  output           cpu_0_data_master_read_data_valid_In1_s1;
  output           cpu_0_data_master_requests_In1_s1;
  output           d1_In1_s1_end_xfer;
  input   [ 15: 0] In1_s1_readdata;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_write;
  input            reset_n;

  wire    [  1: 0] In1_s1_address;
  wire             In1_s1_allgrants;
  wire             In1_s1_allow_new_arb_cycle;
  wire             In1_s1_any_bursting_master_saved_grant;
  wire             In1_s1_any_continuerequest;
  wire             In1_s1_arb_counter_enable;
  reg     [  1: 0] In1_s1_arb_share_counter;
  wire    [  1: 0] In1_s1_arb_share_counter_next_value;
  wire    [  1: 0] In1_s1_arb_share_set_values;
  wire             In1_s1_beginbursttransfer_internal;
  wire             In1_s1_begins_xfer;
  wire             In1_s1_end_xfer;
  wire             In1_s1_firsttransfer;
  wire             In1_s1_grant_vector;
  wire             In1_s1_in_a_read_cycle;
  wire             In1_s1_in_a_write_cycle;
  wire             In1_s1_master_qreq_vector;
  wire             In1_s1_non_bursting_master_requests;
  wire    [ 15: 0] In1_s1_readdata_from_sa;
  wire             In1_s1_reset_n;
  reg              In1_s1_slavearbiterlockenable;
  wire             In1_s1_slavearbiterlockenable2;
  wire             In1_s1_waits_for_read;
  wire             In1_s1_waits_for_write;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_In1_s1;
  wire             cpu_0_data_master_qualified_request_In1_s1;
  wire             cpu_0_data_master_read_data_valid_In1_s1;
  wire             cpu_0_data_master_requests_In1_s1;
  wire             cpu_0_data_master_saved_grant_In1_s1;
  reg              d1_In1_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_In1_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_In1_s1_from_cpu_0_data_master;
  wire             wait_for_In1_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~In1_s1_end_xfer;
    end


  assign In1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_In1_s1));
  //assign In1_s1_readdata_from_sa = In1_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign In1_s1_readdata_from_sa = In1_s1_readdata;

  assign cpu_0_data_master_requests_In1_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h830) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
  //In1_s1_arb_share_counter set values, which is an e_mux
  assign In1_s1_arb_share_set_values = 1;

  //In1_s1_non_bursting_master_requests mux, which is an e_mux
  assign In1_s1_non_bursting_master_requests = cpu_0_data_master_requests_In1_s1;

  //In1_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign In1_s1_any_bursting_master_saved_grant = 0;

  //In1_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign In1_s1_arb_share_counter_next_value = In1_s1_firsttransfer ? (In1_s1_arb_share_set_values - 1) : |In1_s1_arb_share_counter ? (In1_s1_arb_share_counter - 1) : 0;

  //In1_s1_allgrants all slave grants, which is an e_mux
  assign In1_s1_allgrants = |In1_s1_grant_vector;

  //In1_s1_end_xfer assignment, which is an e_assign
  assign In1_s1_end_xfer = ~(In1_s1_waits_for_read | In1_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_In1_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_In1_s1 = In1_s1_end_xfer & (~In1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //In1_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign In1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_In1_s1 & In1_s1_allgrants) | (end_xfer_arb_share_counter_term_In1_s1 & ~In1_s1_non_bursting_master_requests);

  //In1_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          In1_s1_arb_share_counter <= 0;
      else if (In1_s1_arb_counter_enable)
          In1_s1_arb_share_counter <= In1_s1_arb_share_counter_next_value;
    end


  //In1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          In1_s1_slavearbiterlockenable <= 0;
      else if ((|In1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_In1_s1) | (end_xfer_arb_share_counter_term_In1_s1 & ~In1_s1_non_bursting_master_requests))
          In1_s1_slavearbiterlockenable <= |In1_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master In1/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = In1_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //In1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign In1_s1_slavearbiterlockenable2 = |In1_s1_arb_share_counter_next_value;

  //cpu_0/data_master In1/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = In1_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //In1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign In1_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_In1_s1 = cpu_0_data_master_requests_In1_s1;
  //master is always granted when requested
  assign cpu_0_data_master_granted_In1_s1 = cpu_0_data_master_qualified_request_In1_s1;

  //cpu_0/data_master saved-grant In1/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_In1_s1 = cpu_0_data_master_requests_In1_s1;

  //allow new arb cycle for In1/s1, which is an e_assign
  assign In1_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign In1_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign In1_s1_master_qreq_vector = 1;

  //In1_s1_reset_n assignment, which is an e_assign
  assign In1_s1_reset_n = reset_n;

  //In1_s1_firsttransfer first transaction, which is an e_assign
  assign In1_s1_firsttransfer = ~(In1_s1_slavearbiterlockenable & In1_s1_any_continuerequest);

  //In1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign In1_s1_beginbursttransfer_internal = In1_s1_begins_xfer;

  assign shifted_address_to_In1_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //In1_s1_address mux, which is an e_mux
  assign In1_s1_address = shifted_address_to_In1_s1_from_cpu_0_data_master >> 2;

  //d1_In1_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_In1_s1_end_xfer <= 1;
      else if (1)
          d1_In1_s1_end_xfer <= In1_s1_end_xfer;
    end


  //In1_s1_waits_for_read in a cycle, which is an e_mux
  assign In1_s1_waits_for_read = In1_s1_in_a_read_cycle & In1_s1_begins_xfer;

  //In1_s1_in_a_read_cycle assignment, which is an e_assign
  assign In1_s1_in_a_read_cycle = cpu_0_data_master_granted_In1_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = In1_s1_in_a_read_cycle;

  //In1_s1_waits_for_write in a cycle, which is an e_mux
  assign In1_s1_waits_for_write = In1_s1_in_a_write_cycle & 0;

  //In1_s1_in_a_write_cycle assignment, which is an e_assign
  assign In1_s1_in_a_write_cycle = cpu_0_data_master_granted_In1_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = In1_s1_in_a_write_cycle;

  assign wait_for_In1_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module In2_s1_arbitrator (
                           // inputs:
                            In2_s1_readdata,
                            clk,
                            cpu_0_data_master_address_to_slave,
                            cpu_0_data_master_read,
                            cpu_0_data_master_write,
                            reset_n,

                           // outputs:
                            In2_s1_address,
                            In2_s1_readdata_from_sa,
                            In2_s1_reset_n,
                            cpu_0_data_master_granted_In2_s1,
                            cpu_0_data_master_qualified_request_In2_s1,
                            cpu_0_data_master_read_data_valid_In2_s1,
                            cpu_0_data_master_requests_In2_s1,
                            d1_In2_s1_end_xfer
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] In2_s1_address;
  output  [ 15: 0] In2_s1_readdata_from_sa;
  output           In2_s1_reset_n;
  output           cpu_0_data_master_granted_In2_s1;
  output           cpu_0_data_master_qualified_request_In2_s1;
  output           cpu_0_data_master_read_data_valid_In2_s1;
  output           cpu_0_data_master_requests_In2_s1;
  output           d1_In2_s1_end_xfer;
  input   [ 15: 0] In2_s1_readdata;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_write;
  input            reset_n;

  wire    [  1: 0] In2_s1_address;
  wire             In2_s1_allgrants;
  wire             In2_s1_allow_new_arb_cycle;
  wire             In2_s1_any_bursting_master_saved_grant;
  wire             In2_s1_any_continuerequest;
  wire             In2_s1_arb_counter_enable;
  reg     [  1: 0] In2_s1_arb_share_counter;
  wire    [  1: 0] In2_s1_arb_share_counter_next_value;
  wire    [  1: 0] In2_s1_arb_share_set_values;
  wire             In2_s1_beginbursttransfer_internal;
  wire             In2_s1_begins_xfer;
  wire             In2_s1_end_xfer;
  wire             In2_s1_firsttransfer;
  wire             In2_s1_grant_vector;
  wire             In2_s1_in_a_read_cycle;
  wire             In2_s1_in_a_write_cycle;
  wire             In2_s1_master_qreq_vector;
  wire             In2_s1_non_bursting_master_requests;
  wire    [ 15: 0] In2_s1_readdata_from_sa;
  wire             In2_s1_reset_n;
  reg              In2_s1_slavearbiterlockenable;
  wire             In2_s1_slavearbiterlockenable2;
  wire             In2_s1_waits_for_read;
  wire             In2_s1_waits_for_write;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_In2_s1;
  wire             cpu_0_data_master_qualified_request_In2_s1;
  wire             cpu_0_data_master_read_data_valid_In2_s1;
  wire             cpu_0_data_master_requests_In2_s1;
  wire             cpu_0_data_master_saved_grant_In2_s1;
  reg              d1_In2_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_In2_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_In2_s1_from_cpu_0_data_master;
  wire             wait_for_In2_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~In2_s1_end_xfer;
    end


  assign In2_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_In2_s1));
  //assign In2_s1_readdata_from_sa = In2_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign In2_s1_readdata_from_sa = In2_s1_readdata;

  assign cpu_0_data_master_requests_In2_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h860) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
  //In2_s1_arb_share_counter set values, which is an e_mux
  assign In2_s1_arb_share_set_values = 1;

  //In2_s1_non_bursting_master_requests mux, which is an e_mux
  assign In2_s1_non_bursting_master_requests = cpu_0_data_master_requests_In2_s1;

  //In2_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign In2_s1_any_bursting_master_saved_grant = 0;

  //In2_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign In2_s1_arb_share_counter_next_value = In2_s1_firsttransfer ? (In2_s1_arb_share_set_values - 1) : |In2_s1_arb_share_counter ? (In2_s1_arb_share_counter - 1) : 0;

  //In2_s1_allgrants all slave grants, which is an e_mux
  assign In2_s1_allgrants = |In2_s1_grant_vector;

  //In2_s1_end_xfer assignment, which is an e_assign
  assign In2_s1_end_xfer = ~(In2_s1_waits_for_read | In2_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_In2_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_In2_s1 = In2_s1_end_xfer & (~In2_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //In2_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign In2_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_In2_s1 & In2_s1_allgrants) | (end_xfer_arb_share_counter_term_In2_s1 & ~In2_s1_non_bursting_master_requests);

  //In2_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          In2_s1_arb_share_counter <= 0;
      else if (In2_s1_arb_counter_enable)
          In2_s1_arb_share_counter <= In2_s1_arb_share_counter_next_value;
    end


  //In2_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          In2_s1_slavearbiterlockenable <= 0;
      else if ((|In2_s1_master_qreq_vector & end_xfer_arb_share_counter_term_In2_s1) | (end_xfer_arb_share_counter_term_In2_s1 & ~In2_s1_non_bursting_master_requests))
          In2_s1_slavearbiterlockenable <= |In2_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master In2/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = In2_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //In2_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign In2_s1_slavearbiterlockenable2 = |In2_s1_arb_share_counter_next_value;

  //cpu_0/data_master In2/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = In2_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //In2_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign In2_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_In2_s1 = cpu_0_data_master_requests_In2_s1;
  //master is always granted when requested
  assign cpu_0_data_master_granted_In2_s1 = cpu_0_data_master_qualified_request_In2_s1;

  //cpu_0/data_master saved-grant In2/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_In2_s1 = cpu_0_data_master_requests_In2_s1;

  //allow new arb cycle for In2/s1, which is an e_assign
  assign In2_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign In2_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign In2_s1_master_qreq_vector = 1;

  //In2_s1_reset_n assignment, which is an e_assign
  assign In2_s1_reset_n = reset_n;

  //In2_s1_firsttransfer first transaction, which is an e_assign
  assign In2_s1_firsttransfer = ~(In2_s1_slavearbiterlockenable & In2_s1_any_continuerequest);

  //In2_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign In2_s1_beginbursttransfer_internal = In2_s1_begins_xfer;

  assign shifted_address_to_In2_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //In2_s1_address mux, which is an e_mux
  assign In2_s1_address = shifted_address_to_In2_s1_from_cpu_0_data_master >> 2;

  //d1_In2_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_In2_s1_end_xfer <= 1;
      else if (1)
          d1_In2_s1_end_xfer <= In2_s1_end_xfer;
    end


  //In2_s1_waits_for_read in a cycle, which is an e_mux
  assign In2_s1_waits_for_read = In2_s1_in_a_read_cycle & In2_s1_begins_xfer;

  //In2_s1_in_a_read_cycle assignment, which is an e_assign
  assign In2_s1_in_a_read_cycle = cpu_0_data_master_granted_In2_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = In2_s1_in_a_read_cycle;

  //In2_s1_waits_for_write in a cycle, which is an e_mux
  assign In2_s1_waits_for_write = In2_s1_in_a_write_cycle & 0;

  //In2_s1_in_a_write_cycle assignment, which is an e_assign
  assign In2_s1_in_a_write_cycle = cpu_0_data_master_granted_In2_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = In2_s1_in_a_write_cycle;

  assign wait_for_In2_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Out0_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_0_data_master_address_to_slave,
                             cpu_0_data_master_read,
                             cpu_0_data_master_waitrequest,
                             cpu_0_data_master_write,
                             cpu_0_data_master_writedata,
                             reset_n,

                            // outputs:
                             Out0_s1_address,
                             Out0_s1_chipselect,
                             Out0_s1_reset_n,
                             Out0_s1_write_n,
                             Out0_s1_writedata,
                             cpu_0_data_master_granted_Out0_s1,
                             cpu_0_data_master_qualified_request_Out0_s1,
                             cpu_0_data_master_read_data_valid_Out0_s1,
                             cpu_0_data_master_requests_Out0_s1,
                             d1_Out0_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Out0_s1_address;
  output           Out0_s1_chipselect;
  output           Out0_s1_reset_n;
  output           Out0_s1_write_n;
  output           Out0_s1_writedata;
  output           cpu_0_data_master_granted_Out0_s1;
  output           cpu_0_data_master_qualified_request_Out0_s1;
  output           cpu_0_data_master_read_data_valid_Out0_s1;
  output           cpu_0_data_master_requests_Out0_s1;
  output           d1_Out0_s1_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] Out0_s1_address;
  wire             Out0_s1_allgrants;
  wire             Out0_s1_allow_new_arb_cycle;
  wire             Out0_s1_any_bursting_master_saved_grant;
  wire             Out0_s1_any_continuerequest;
  wire             Out0_s1_arb_counter_enable;
  reg     [  1: 0] Out0_s1_arb_share_counter;
  wire    [  1: 0] Out0_s1_arb_share_counter_next_value;
  wire    [  1: 0] Out0_s1_arb_share_set_values;
  wire             Out0_s1_beginbursttransfer_internal;
  wire             Out0_s1_begins_xfer;
  wire             Out0_s1_chipselect;
  wire             Out0_s1_end_xfer;
  wire             Out0_s1_firsttransfer;
  wire             Out0_s1_grant_vector;
  wire             Out0_s1_in_a_read_cycle;
  wire             Out0_s1_in_a_write_cycle;
  wire             Out0_s1_master_qreq_vector;
  wire             Out0_s1_non_bursting_master_requests;
  wire             Out0_s1_reset_n;
  reg              Out0_s1_slavearbiterlockenable;
  wire             Out0_s1_slavearbiterlockenable2;
  wire             Out0_s1_waits_for_read;
  wire             Out0_s1_waits_for_write;
  wire             Out0_s1_write_n;
  wire             Out0_s1_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_Out0_s1;
  wire             cpu_0_data_master_qualified_request_Out0_s1;
  wire             cpu_0_data_master_read_data_valid_Out0_s1;
  wire             cpu_0_data_master_requests_Out0_s1;
  wire             cpu_0_data_master_saved_grant_Out0_s1;
  reg              d1_Out0_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_Out0_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_Out0_s1_from_cpu_0_data_master;
  wire             wait_for_Out0_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Out0_s1_end_xfer;
    end


  assign Out0_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Out0_s1));
  assign cpu_0_data_master_requests_Out0_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h870) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_write;
  //Out0_s1_arb_share_counter set values, which is an e_mux
  assign Out0_s1_arb_share_set_values = 1;

  //Out0_s1_non_bursting_master_requests mux, which is an e_mux
  assign Out0_s1_non_bursting_master_requests = cpu_0_data_master_requests_Out0_s1;

  //Out0_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Out0_s1_any_bursting_master_saved_grant = 0;

  //Out0_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Out0_s1_arb_share_counter_next_value = Out0_s1_firsttransfer ? (Out0_s1_arb_share_set_values - 1) : |Out0_s1_arb_share_counter ? (Out0_s1_arb_share_counter - 1) : 0;

  //Out0_s1_allgrants all slave grants, which is an e_mux
  assign Out0_s1_allgrants = |Out0_s1_grant_vector;

  //Out0_s1_end_xfer assignment, which is an e_assign
  assign Out0_s1_end_xfer = ~(Out0_s1_waits_for_read | Out0_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Out0_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Out0_s1 = Out0_s1_end_xfer & (~Out0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Out0_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Out0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Out0_s1 & Out0_s1_allgrants) | (end_xfer_arb_share_counter_term_Out0_s1 & ~Out0_s1_non_bursting_master_requests);

  //Out0_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out0_s1_arb_share_counter <= 0;
      else if (Out0_s1_arb_counter_enable)
          Out0_s1_arb_share_counter <= Out0_s1_arb_share_counter_next_value;
    end


  //Out0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out0_s1_slavearbiterlockenable <= 0;
      else if ((|Out0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Out0_s1) | (end_xfer_arb_share_counter_term_Out0_s1 & ~Out0_s1_non_bursting_master_requests))
          Out0_s1_slavearbiterlockenable <= |Out0_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master Out0/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = Out0_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //Out0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Out0_s1_slavearbiterlockenable2 = |Out0_s1_arb_share_counter_next_value;

  //cpu_0/data_master Out0/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = Out0_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //Out0_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Out0_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_Out0_s1 = cpu_0_data_master_requests_Out0_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  //Out0_s1_writedata mux, which is an e_mux
  assign Out0_s1_writedata = cpu_0_data_master_writedata;

  //master is always granted when requested
  assign cpu_0_data_master_granted_Out0_s1 = cpu_0_data_master_qualified_request_Out0_s1;

  //cpu_0/data_master saved-grant Out0/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_Out0_s1 = cpu_0_data_master_requests_Out0_s1;

  //allow new arb cycle for Out0/s1, which is an e_assign
  assign Out0_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Out0_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Out0_s1_master_qreq_vector = 1;

  //Out0_s1_reset_n assignment, which is an e_assign
  assign Out0_s1_reset_n = reset_n;

  assign Out0_s1_chipselect = cpu_0_data_master_granted_Out0_s1;
  //Out0_s1_firsttransfer first transaction, which is an e_assign
  assign Out0_s1_firsttransfer = ~(Out0_s1_slavearbiterlockenable & Out0_s1_any_continuerequest);

  //Out0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Out0_s1_beginbursttransfer_internal = Out0_s1_begins_xfer;

  //~Out0_s1_write_n assignment, which is an e_mux
  assign Out0_s1_write_n = ~(cpu_0_data_master_granted_Out0_s1 & cpu_0_data_master_write);

  assign shifted_address_to_Out0_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //Out0_s1_address mux, which is an e_mux
  assign Out0_s1_address = shifted_address_to_Out0_s1_from_cpu_0_data_master >> 2;

  //d1_Out0_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Out0_s1_end_xfer <= 1;
      else if (1)
          d1_Out0_s1_end_xfer <= Out0_s1_end_xfer;
    end


  //Out0_s1_waits_for_read in a cycle, which is an e_mux
  assign Out0_s1_waits_for_read = Out0_s1_in_a_read_cycle & Out0_s1_begins_xfer;

  //Out0_s1_in_a_read_cycle assignment, which is an e_assign
  assign Out0_s1_in_a_read_cycle = cpu_0_data_master_granted_Out0_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Out0_s1_in_a_read_cycle;

  //Out0_s1_waits_for_write in a cycle, which is an e_mux
  assign Out0_s1_waits_for_write = Out0_s1_in_a_write_cycle & 0;

  //Out0_s1_in_a_write_cycle assignment, which is an e_assign
  assign Out0_s1_in_a_write_cycle = cpu_0_data_master_granted_Out0_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Out0_s1_in_a_write_cycle;

  assign wait_for_Out0_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Out1_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_0_data_master_address_to_slave,
                             cpu_0_data_master_read,
                             cpu_0_data_master_waitrequest,
                             cpu_0_data_master_write,
                             cpu_0_data_master_writedata,
                             reset_n,

                            // outputs:
                             Out1_s1_address,
                             Out1_s1_chipselect,
                             Out1_s1_reset_n,
                             Out1_s1_write_n,
                             Out1_s1_writedata,
                             cpu_0_data_master_granted_Out1_s1,
                             cpu_0_data_master_qualified_request_Out1_s1,
                             cpu_0_data_master_read_data_valid_Out1_s1,
                             cpu_0_data_master_requests_Out1_s1,
                             d1_Out1_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Out1_s1_address;
  output           Out1_s1_chipselect;
  output           Out1_s1_reset_n;
  output           Out1_s1_write_n;
  output  [ 17: 0] Out1_s1_writedata;
  output           cpu_0_data_master_granted_Out1_s1;
  output           cpu_0_data_master_qualified_request_Out1_s1;
  output           cpu_0_data_master_read_data_valid_Out1_s1;
  output           cpu_0_data_master_requests_Out1_s1;
  output           d1_Out1_s1_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] Out1_s1_address;
  wire             Out1_s1_allgrants;
  wire             Out1_s1_allow_new_arb_cycle;
  wire             Out1_s1_any_bursting_master_saved_grant;
  wire             Out1_s1_any_continuerequest;
  wire             Out1_s1_arb_counter_enable;
  reg     [  1: 0] Out1_s1_arb_share_counter;
  wire    [  1: 0] Out1_s1_arb_share_counter_next_value;
  wire    [  1: 0] Out1_s1_arb_share_set_values;
  wire             Out1_s1_beginbursttransfer_internal;
  wire             Out1_s1_begins_xfer;
  wire             Out1_s1_chipselect;
  wire             Out1_s1_end_xfer;
  wire             Out1_s1_firsttransfer;
  wire             Out1_s1_grant_vector;
  wire             Out1_s1_in_a_read_cycle;
  wire             Out1_s1_in_a_write_cycle;
  wire             Out1_s1_master_qreq_vector;
  wire             Out1_s1_non_bursting_master_requests;
  wire             Out1_s1_reset_n;
  reg              Out1_s1_slavearbiterlockenable;
  wire             Out1_s1_slavearbiterlockenable2;
  wire             Out1_s1_waits_for_read;
  wire             Out1_s1_waits_for_write;
  wire             Out1_s1_write_n;
  wire    [ 17: 0] Out1_s1_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_Out1_s1;
  wire             cpu_0_data_master_qualified_request_Out1_s1;
  wire             cpu_0_data_master_read_data_valid_Out1_s1;
  wire             cpu_0_data_master_requests_Out1_s1;
  wire             cpu_0_data_master_saved_grant_Out1_s1;
  reg              d1_Out1_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_Out1_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_Out1_s1_from_cpu_0_data_master;
  wire             wait_for_Out1_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Out1_s1_end_xfer;
    end


  assign Out1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Out1_s1));
  assign cpu_0_data_master_requests_Out1_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h880) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_write;
  //Out1_s1_arb_share_counter set values, which is an e_mux
  assign Out1_s1_arb_share_set_values = 1;

  //Out1_s1_non_bursting_master_requests mux, which is an e_mux
  assign Out1_s1_non_bursting_master_requests = cpu_0_data_master_requests_Out1_s1;

  //Out1_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Out1_s1_any_bursting_master_saved_grant = 0;

  //Out1_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Out1_s1_arb_share_counter_next_value = Out1_s1_firsttransfer ? (Out1_s1_arb_share_set_values - 1) : |Out1_s1_arb_share_counter ? (Out1_s1_arb_share_counter - 1) : 0;

  //Out1_s1_allgrants all slave grants, which is an e_mux
  assign Out1_s1_allgrants = |Out1_s1_grant_vector;

  //Out1_s1_end_xfer assignment, which is an e_assign
  assign Out1_s1_end_xfer = ~(Out1_s1_waits_for_read | Out1_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Out1_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Out1_s1 = Out1_s1_end_xfer & (~Out1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Out1_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Out1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Out1_s1 & Out1_s1_allgrants) | (end_xfer_arb_share_counter_term_Out1_s1 & ~Out1_s1_non_bursting_master_requests);

  //Out1_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out1_s1_arb_share_counter <= 0;
      else if (Out1_s1_arb_counter_enable)
          Out1_s1_arb_share_counter <= Out1_s1_arb_share_counter_next_value;
    end


  //Out1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out1_s1_slavearbiterlockenable <= 0;
      else if ((|Out1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Out1_s1) | (end_xfer_arb_share_counter_term_Out1_s1 & ~Out1_s1_non_bursting_master_requests))
          Out1_s1_slavearbiterlockenable <= |Out1_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master Out1/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = Out1_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //Out1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Out1_s1_slavearbiterlockenable2 = |Out1_s1_arb_share_counter_next_value;

  //cpu_0/data_master Out1/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = Out1_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //Out1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Out1_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_Out1_s1 = cpu_0_data_master_requests_Out1_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  //Out1_s1_writedata mux, which is an e_mux
  assign Out1_s1_writedata = cpu_0_data_master_writedata;

  //master is always granted when requested
  assign cpu_0_data_master_granted_Out1_s1 = cpu_0_data_master_qualified_request_Out1_s1;

  //cpu_0/data_master saved-grant Out1/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_Out1_s1 = cpu_0_data_master_requests_Out1_s1;

  //allow new arb cycle for Out1/s1, which is an e_assign
  assign Out1_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Out1_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Out1_s1_master_qreq_vector = 1;

  //Out1_s1_reset_n assignment, which is an e_assign
  assign Out1_s1_reset_n = reset_n;

  assign Out1_s1_chipselect = cpu_0_data_master_granted_Out1_s1;
  //Out1_s1_firsttransfer first transaction, which is an e_assign
  assign Out1_s1_firsttransfer = ~(Out1_s1_slavearbiterlockenable & Out1_s1_any_continuerequest);

  //Out1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Out1_s1_beginbursttransfer_internal = Out1_s1_begins_xfer;

  //~Out1_s1_write_n assignment, which is an e_mux
  assign Out1_s1_write_n = ~(cpu_0_data_master_granted_Out1_s1 & cpu_0_data_master_write);

  assign shifted_address_to_Out1_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //Out1_s1_address mux, which is an e_mux
  assign Out1_s1_address = shifted_address_to_Out1_s1_from_cpu_0_data_master >> 2;

  //d1_Out1_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Out1_s1_end_xfer <= 1;
      else if (1)
          d1_Out1_s1_end_xfer <= Out1_s1_end_xfer;
    end


  //Out1_s1_waits_for_read in a cycle, which is an e_mux
  assign Out1_s1_waits_for_read = Out1_s1_in_a_read_cycle & Out1_s1_begins_xfer;

  //Out1_s1_in_a_read_cycle assignment, which is an e_assign
  assign Out1_s1_in_a_read_cycle = cpu_0_data_master_granted_Out1_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Out1_s1_in_a_read_cycle;

  //Out1_s1_waits_for_write in a cycle, which is an e_mux
  assign Out1_s1_waits_for_write = Out1_s1_in_a_write_cycle & 0;

  //Out1_s1_in_a_write_cycle assignment, which is an e_assign
  assign Out1_s1_in_a_write_cycle = cpu_0_data_master_granted_Out1_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Out1_s1_in_a_write_cycle;

  assign wait_for_Out1_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Out2_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_0_data_master_address_to_slave,
                             cpu_0_data_master_read,
                             cpu_0_data_master_waitrequest,
                             cpu_0_data_master_write,
                             cpu_0_data_master_writedata,
                             reset_n,

                            // outputs:
                             Out2_s1_address,
                             Out2_s1_chipselect,
                             Out2_s1_reset_n,
                             Out2_s1_write_n,
                             Out2_s1_writedata,
                             cpu_0_data_master_granted_Out2_s1,
                             cpu_0_data_master_qualified_request_Out2_s1,
                             cpu_0_data_master_read_data_valid_Out2_s1,
                             cpu_0_data_master_requests_Out2_s1,
                             d1_Out2_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Out2_s1_address;
  output           Out2_s1_chipselect;
  output           Out2_s1_reset_n;
  output           Out2_s1_write_n;
  output  [  9: 0] Out2_s1_writedata;
  output           cpu_0_data_master_granted_Out2_s1;
  output           cpu_0_data_master_qualified_request_Out2_s1;
  output           cpu_0_data_master_read_data_valid_Out2_s1;
  output           cpu_0_data_master_requests_Out2_s1;
  output           d1_Out2_s1_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] Out2_s1_address;
  wire             Out2_s1_allgrants;
  wire             Out2_s1_allow_new_arb_cycle;
  wire             Out2_s1_any_bursting_master_saved_grant;
  wire             Out2_s1_any_continuerequest;
  wire             Out2_s1_arb_counter_enable;
  reg     [  1: 0] Out2_s1_arb_share_counter;
  wire    [  1: 0] Out2_s1_arb_share_counter_next_value;
  wire    [  1: 0] Out2_s1_arb_share_set_values;
  wire             Out2_s1_beginbursttransfer_internal;
  wire             Out2_s1_begins_xfer;
  wire             Out2_s1_chipselect;
  wire             Out2_s1_end_xfer;
  wire             Out2_s1_firsttransfer;
  wire             Out2_s1_grant_vector;
  wire             Out2_s1_in_a_read_cycle;
  wire             Out2_s1_in_a_write_cycle;
  wire             Out2_s1_master_qreq_vector;
  wire             Out2_s1_non_bursting_master_requests;
  wire             Out2_s1_reset_n;
  reg              Out2_s1_slavearbiterlockenable;
  wire             Out2_s1_slavearbiterlockenable2;
  wire             Out2_s1_waits_for_read;
  wire             Out2_s1_waits_for_write;
  wire             Out2_s1_write_n;
  wire    [  9: 0] Out2_s1_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_Out2_s1;
  wire             cpu_0_data_master_qualified_request_Out2_s1;
  wire             cpu_0_data_master_read_data_valid_Out2_s1;
  wire             cpu_0_data_master_requests_Out2_s1;
  wire             cpu_0_data_master_saved_grant_Out2_s1;
  reg              d1_Out2_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_Out2_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_Out2_s1_from_cpu_0_data_master;
  wire             wait_for_Out2_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Out2_s1_end_xfer;
    end


  assign Out2_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Out2_s1));
  assign cpu_0_data_master_requests_Out2_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h890) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_write;
  //Out2_s1_arb_share_counter set values, which is an e_mux
  assign Out2_s1_arb_share_set_values = 1;

  //Out2_s1_non_bursting_master_requests mux, which is an e_mux
  assign Out2_s1_non_bursting_master_requests = cpu_0_data_master_requests_Out2_s1;

  //Out2_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Out2_s1_any_bursting_master_saved_grant = 0;

  //Out2_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Out2_s1_arb_share_counter_next_value = Out2_s1_firsttransfer ? (Out2_s1_arb_share_set_values - 1) : |Out2_s1_arb_share_counter ? (Out2_s1_arb_share_counter - 1) : 0;

  //Out2_s1_allgrants all slave grants, which is an e_mux
  assign Out2_s1_allgrants = |Out2_s1_grant_vector;

  //Out2_s1_end_xfer assignment, which is an e_assign
  assign Out2_s1_end_xfer = ~(Out2_s1_waits_for_read | Out2_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Out2_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Out2_s1 = Out2_s1_end_xfer & (~Out2_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Out2_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Out2_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Out2_s1 & Out2_s1_allgrants) | (end_xfer_arb_share_counter_term_Out2_s1 & ~Out2_s1_non_bursting_master_requests);

  //Out2_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out2_s1_arb_share_counter <= 0;
      else if (Out2_s1_arb_counter_enable)
          Out2_s1_arb_share_counter <= Out2_s1_arb_share_counter_next_value;
    end


  //Out2_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out2_s1_slavearbiterlockenable <= 0;
      else if ((|Out2_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Out2_s1) | (end_xfer_arb_share_counter_term_Out2_s1 & ~Out2_s1_non_bursting_master_requests))
          Out2_s1_slavearbiterlockenable <= |Out2_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master Out2/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = Out2_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //Out2_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Out2_s1_slavearbiterlockenable2 = |Out2_s1_arb_share_counter_next_value;

  //cpu_0/data_master Out2/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = Out2_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //Out2_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Out2_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_Out2_s1 = cpu_0_data_master_requests_Out2_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  //Out2_s1_writedata mux, which is an e_mux
  assign Out2_s1_writedata = cpu_0_data_master_writedata;

  //master is always granted when requested
  assign cpu_0_data_master_granted_Out2_s1 = cpu_0_data_master_qualified_request_Out2_s1;

  //cpu_0/data_master saved-grant Out2/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_Out2_s1 = cpu_0_data_master_requests_Out2_s1;

  //allow new arb cycle for Out2/s1, which is an e_assign
  assign Out2_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Out2_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Out2_s1_master_qreq_vector = 1;

  //Out2_s1_reset_n assignment, which is an e_assign
  assign Out2_s1_reset_n = reset_n;

  assign Out2_s1_chipselect = cpu_0_data_master_granted_Out2_s1;
  //Out2_s1_firsttransfer first transaction, which is an e_assign
  assign Out2_s1_firsttransfer = ~(Out2_s1_slavearbiterlockenable & Out2_s1_any_continuerequest);

  //Out2_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Out2_s1_beginbursttransfer_internal = Out2_s1_begins_xfer;

  //~Out2_s1_write_n assignment, which is an e_mux
  assign Out2_s1_write_n = ~(cpu_0_data_master_granted_Out2_s1 & cpu_0_data_master_write);

  assign shifted_address_to_Out2_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //Out2_s1_address mux, which is an e_mux
  assign Out2_s1_address = shifted_address_to_Out2_s1_from_cpu_0_data_master >> 2;

  //d1_Out2_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Out2_s1_end_xfer <= 1;
      else if (1)
          d1_Out2_s1_end_xfer <= Out2_s1_end_xfer;
    end


  //Out2_s1_waits_for_read in a cycle, which is an e_mux
  assign Out2_s1_waits_for_read = Out2_s1_in_a_read_cycle & Out2_s1_begins_xfer;

  //Out2_s1_in_a_read_cycle assignment, which is an e_assign
  assign Out2_s1_in_a_read_cycle = cpu_0_data_master_granted_Out2_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Out2_s1_in_a_read_cycle;

  //Out2_s1_waits_for_write in a cycle, which is an e_mux
  assign Out2_s1_waits_for_write = Out2_s1_in_a_write_cycle & 0;

  //Out2_s1_in_a_write_cycle assignment, which is an e_assign
  assign Out2_s1_in_a_write_cycle = cpu_0_data_master_granted_Out2_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Out2_s1_in_a_write_cycle;

  assign wait_for_Out2_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Out3_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_0_data_master_address_to_slave,
                             cpu_0_data_master_read,
                             cpu_0_data_master_waitrequest,
                             cpu_0_data_master_write,
                             cpu_0_data_master_writedata,
                             reset_n,

                            // outputs:
                             Out3_s1_address,
                             Out3_s1_chipselect,
                             Out3_s1_reset_n,
                             Out3_s1_write_n,
                             Out3_s1_writedata,
                             cpu_0_data_master_granted_Out3_s1,
                             cpu_0_data_master_qualified_request_Out3_s1,
                             cpu_0_data_master_read_data_valid_Out3_s1,
                             cpu_0_data_master_requests_Out3_s1,
                             d1_Out3_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Out3_s1_address;
  output           Out3_s1_chipselect;
  output           Out3_s1_reset_n;
  output           Out3_s1_write_n;
  output  [  9: 0] Out3_s1_writedata;
  output           cpu_0_data_master_granted_Out3_s1;
  output           cpu_0_data_master_qualified_request_Out3_s1;
  output           cpu_0_data_master_read_data_valid_Out3_s1;
  output           cpu_0_data_master_requests_Out3_s1;
  output           d1_Out3_s1_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] Out3_s1_address;
  wire             Out3_s1_allgrants;
  wire             Out3_s1_allow_new_arb_cycle;
  wire             Out3_s1_any_bursting_master_saved_grant;
  wire             Out3_s1_any_continuerequest;
  wire             Out3_s1_arb_counter_enable;
  reg     [  1: 0] Out3_s1_arb_share_counter;
  wire    [  1: 0] Out3_s1_arb_share_counter_next_value;
  wire    [  1: 0] Out3_s1_arb_share_set_values;
  wire             Out3_s1_beginbursttransfer_internal;
  wire             Out3_s1_begins_xfer;
  wire             Out3_s1_chipselect;
  wire             Out3_s1_end_xfer;
  wire             Out3_s1_firsttransfer;
  wire             Out3_s1_grant_vector;
  wire             Out3_s1_in_a_read_cycle;
  wire             Out3_s1_in_a_write_cycle;
  wire             Out3_s1_master_qreq_vector;
  wire             Out3_s1_non_bursting_master_requests;
  wire             Out3_s1_reset_n;
  reg              Out3_s1_slavearbiterlockenable;
  wire             Out3_s1_slavearbiterlockenable2;
  wire             Out3_s1_waits_for_read;
  wire             Out3_s1_waits_for_write;
  wire             Out3_s1_write_n;
  wire    [  9: 0] Out3_s1_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_Out3_s1;
  wire             cpu_0_data_master_qualified_request_Out3_s1;
  wire             cpu_0_data_master_read_data_valid_Out3_s1;
  wire             cpu_0_data_master_requests_Out3_s1;
  wire             cpu_0_data_master_saved_grant_Out3_s1;
  reg              d1_Out3_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_Out3_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_Out3_s1_from_cpu_0_data_master;
  wire             wait_for_Out3_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Out3_s1_end_xfer;
    end


  assign Out3_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Out3_s1));
  assign cpu_0_data_master_requests_Out3_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h8a0) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_write;
  //Out3_s1_arb_share_counter set values, which is an e_mux
  assign Out3_s1_arb_share_set_values = 1;

  //Out3_s1_non_bursting_master_requests mux, which is an e_mux
  assign Out3_s1_non_bursting_master_requests = cpu_0_data_master_requests_Out3_s1;

  //Out3_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Out3_s1_any_bursting_master_saved_grant = 0;

  //Out3_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Out3_s1_arb_share_counter_next_value = Out3_s1_firsttransfer ? (Out3_s1_arb_share_set_values - 1) : |Out3_s1_arb_share_counter ? (Out3_s1_arb_share_counter - 1) : 0;

  //Out3_s1_allgrants all slave grants, which is an e_mux
  assign Out3_s1_allgrants = |Out3_s1_grant_vector;

  //Out3_s1_end_xfer assignment, which is an e_assign
  assign Out3_s1_end_xfer = ~(Out3_s1_waits_for_read | Out3_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Out3_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Out3_s1 = Out3_s1_end_xfer & (~Out3_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Out3_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Out3_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Out3_s1 & Out3_s1_allgrants) | (end_xfer_arb_share_counter_term_Out3_s1 & ~Out3_s1_non_bursting_master_requests);

  //Out3_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out3_s1_arb_share_counter <= 0;
      else if (Out3_s1_arb_counter_enable)
          Out3_s1_arb_share_counter <= Out3_s1_arb_share_counter_next_value;
    end


  //Out3_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out3_s1_slavearbiterlockenable <= 0;
      else if ((|Out3_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Out3_s1) | (end_xfer_arb_share_counter_term_Out3_s1 & ~Out3_s1_non_bursting_master_requests))
          Out3_s1_slavearbiterlockenable <= |Out3_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master Out3/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = Out3_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //Out3_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Out3_s1_slavearbiterlockenable2 = |Out3_s1_arb_share_counter_next_value;

  //cpu_0/data_master Out3/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = Out3_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //Out3_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Out3_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_Out3_s1 = cpu_0_data_master_requests_Out3_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  //Out3_s1_writedata mux, which is an e_mux
  assign Out3_s1_writedata = cpu_0_data_master_writedata;

  //master is always granted when requested
  assign cpu_0_data_master_granted_Out3_s1 = cpu_0_data_master_qualified_request_Out3_s1;

  //cpu_0/data_master saved-grant Out3/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_Out3_s1 = cpu_0_data_master_requests_Out3_s1;

  //allow new arb cycle for Out3/s1, which is an e_assign
  assign Out3_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Out3_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Out3_s1_master_qreq_vector = 1;

  //Out3_s1_reset_n assignment, which is an e_assign
  assign Out3_s1_reset_n = reset_n;

  assign Out3_s1_chipselect = cpu_0_data_master_granted_Out3_s1;
  //Out3_s1_firsttransfer first transaction, which is an e_assign
  assign Out3_s1_firsttransfer = ~(Out3_s1_slavearbiterlockenable & Out3_s1_any_continuerequest);

  //Out3_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Out3_s1_beginbursttransfer_internal = Out3_s1_begins_xfer;

  //~Out3_s1_write_n assignment, which is an e_mux
  assign Out3_s1_write_n = ~(cpu_0_data_master_granted_Out3_s1 & cpu_0_data_master_write);

  assign shifted_address_to_Out3_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //Out3_s1_address mux, which is an e_mux
  assign Out3_s1_address = shifted_address_to_Out3_s1_from_cpu_0_data_master >> 2;

  //d1_Out3_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Out3_s1_end_xfer <= 1;
      else if (1)
          d1_Out3_s1_end_xfer <= Out3_s1_end_xfer;
    end


  //Out3_s1_waits_for_read in a cycle, which is an e_mux
  assign Out3_s1_waits_for_read = Out3_s1_in_a_read_cycle & Out3_s1_begins_xfer;

  //Out3_s1_in_a_read_cycle assignment, which is an e_assign
  assign Out3_s1_in_a_read_cycle = cpu_0_data_master_granted_Out3_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Out3_s1_in_a_read_cycle;

  //Out3_s1_waits_for_write in a cycle, which is an e_mux
  assign Out3_s1_waits_for_write = Out3_s1_in_a_write_cycle & 0;

  //Out3_s1_in_a_write_cycle assignment, which is an e_assign
  assign Out3_s1_in_a_write_cycle = cpu_0_data_master_granted_Out3_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Out3_s1_in_a_write_cycle;

  assign wait_for_Out3_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Out4_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_0_data_master_address_to_slave,
                             cpu_0_data_master_read,
                             cpu_0_data_master_waitrequest,
                             cpu_0_data_master_write,
                             cpu_0_data_master_writedata,
                             reset_n,

                            // outputs:
                             Out4_s1_address,
                             Out4_s1_chipselect,
                             Out4_s1_reset_n,
                             Out4_s1_write_n,
                             Out4_s1_writedata,
                             cpu_0_data_master_granted_Out4_s1,
                             cpu_0_data_master_qualified_request_Out4_s1,
                             cpu_0_data_master_read_data_valid_Out4_s1,
                             cpu_0_data_master_requests_Out4_s1,
                             d1_Out4_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Out4_s1_address;
  output           Out4_s1_chipselect;
  output           Out4_s1_reset_n;
  output           Out4_s1_write_n;
  output  [  9: 0] Out4_s1_writedata;
  output           cpu_0_data_master_granted_Out4_s1;
  output           cpu_0_data_master_qualified_request_Out4_s1;
  output           cpu_0_data_master_read_data_valid_Out4_s1;
  output           cpu_0_data_master_requests_Out4_s1;
  output           d1_Out4_s1_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] Out4_s1_address;
  wire             Out4_s1_allgrants;
  wire             Out4_s1_allow_new_arb_cycle;
  wire             Out4_s1_any_bursting_master_saved_grant;
  wire             Out4_s1_any_continuerequest;
  wire             Out4_s1_arb_counter_enable;
  reg     [  1: 0] Out4_s1_arb_share_counter;
  wire    [  1: 0] Out4_s1_arb_share_counter_next_value;
  wire    [  1: 0] Out4_s1_arb_share_set_values;
  wire             Out4_s1_beginbursttransfer_internal;
  wire             Out4_s1_begins_xfer;
  wire             Out4_s1_chipselect;
  wire             Out4_s1_end_xfer;
  wire             Out4_s1_firsttransfer;
  wire             Out4_s1_grant_vector;
  wire             Out4_s1_in_a_read_cycle;
  wire             Out4_s1_in_a_write_cycle;
  wire             Out4_s1_master_qreq_vector;
  wire             Out4_s1_non_bursting_master_requests;
  wire             Out4_s1_reset_n;
  reg              Out4_s1_slavearbiterlockenable;
  wire             Out4_s1_slavearbiterlockenable2;
  wire             Out4_s1_waits_for_read;
  wire             Out4_s1_waits_for_write;
  wire             Out4_s1_write_n;
  wire    [  9: 0] Out4_s1_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_Out4_s1;
  wire             cpu_0_data_master_qualified_request_Out4_s1;
  wire             cpu_0_data_master_read_data_valid_Out4_s1;
  wire             cpu_0_data_master_requests_Out4_s1;
  wire             cpu_0_data_master_saved_grant_Out4_s1;
  reg              d1_Out4_s1_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_Out4_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 19: 0] shifted_address_to_Out4_s1_from_cpu_0_data_master;
  wire             wait_for_Out4_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Out4_s1_end_xfer;
    end


  assign Out4_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Out4_s1));
  assign cpu_0_data_master_requests_Out4_s1 = (({cpu_0_data_master_address_to_slave[19 : 4] , 4'b0} == 20'h8b0) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_write;
  //Out4_s1_arb_share_counter set values, which is an e_mux
  assign Out4_s1_arb_share_set_values = 1;

  //Out4_s1_non_bursting_master_requests mux, which is an e_mux
  assign Out4_s1_non_bursting_master_requests = cpu_0_data_master_requests_Out4_s1;

  //Out4_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Out4_s1_any_bursting_master_saved_grant = 0;

  //Out4_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Out4_s1_arb_share_counter_next_value = Out4_s1_firsttransfer ? (Out4_s1_arb_share_set_values - 1) : |Out4_s1_arb_share_counter ? (Out4_s1_arb_share_counter - 1) : 0;

  //Out4_s1_allgrants all slave grants, which is an e_mux
  assign Out4_s1_allgrants = |Out4_s1_grant_vector;

  //Out4_s1_end_xfer assignment, which is an e_assign
  assign Out4_s1_end_xfer = ~(Out4_s1_waits_for_read | Out4_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Out4_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Out4_s1 = Out4_s1_end_xfer & (~Out4_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Out4_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Out4_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Out4_s1 & Out4_s1_allgrants) | (end_xfer_arb_share_counter_term_Out4_s1 & ~Out4_s1_non_bursting_master_requests);

  //Out4_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out4_s1_arb_share_counter <= 0;
      else if (Out4_s1_arb_counter_enable)
          Out4_s1_arb_share_counter <= Out4_s1_arb_share_counter_next_value;
    end


  //Out4_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Out4_s1_slavearbiterlockenable <= 0;
      else if ((|Out4_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Out4_s1) | (end_xfer_arb_share_counter_term_Out4_s1 & ~Out4_s1_non_bursting_master_requests))
          Out4_s1_slavearbiterlockenable <= |Out4_s1_arb_share_counter_next_value;
    end


  //cpu_0/data_master Out4/s1 arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = Out4_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //Out4_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Out4_s1_slavearbiterlockenable2 = |Out4_s1_arb_share_counter_next_value;

  //cpu_0/data_master Out4/s1 arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = Out4_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //Out4_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Out4_s1_any_continuerequest = 1;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 1;

  assign cpu_0_data_master_qualified_request_Out4_s1 = cpu_0_data_master_requests_Out4_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  //Out4_s1_writedata mux, which is an e_mux
  assign Out4_s1_writedata = cpu_0_data_master_writedata;

  //master is always granted when requested
  assign cpu_0_data_master_granted_Out4_s1 = cpu_0_data_master_qualified_request_Out4_s1;

  //cpu_0/data_master saved-grant Out4/s1, which is an e_assign
  assign cpu_0_data_master_saved_grant_Out4_s1 = cpu_0_data_master_requests_Out4_s1;

  //allow new arb cycle for Out4/s1, which is an e_assign
  assign Out4_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Out4_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Out4_s1_master_qreq_vector = 1;

  //Out4_s1_reset_n assignment, which is an e_assign
  assign Out4_s1_reset_n = reset_n;

  assign Out4_s1_chipselect = cpu_0_data_master_granted_Out4_s1;
  //Out4_s1_firsttransfer first transaction, which is an e_assign
  assign Out4_s1_firsttransfer = ~(Out4_s1_slavearbiterlockenable & Out4_s1_any_continuerequest);

  //Out4_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Out4_s1_beginbursttransfer_internal = Out4_s1_begins_xfer;

  //~Out4_s1_write_n assignment, which is an e_mux
  assign Out4_s1_write_n = ~(cpu_0_data_master_granted_Out4_s1 & cpu_0_data_master_write);

  assign shifted_address_to_Out4_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //Out4_s1_address mux, which is an e_mux
  assign Out4_s1_address = shifted_address_to_Out4_s1_from_cpu_0_data_master >> 2;

  //d1_Out4_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Out4_s1_end_xfer <= 1;
      else if (1)
          d1_Out4_s1_end_xfer <= Out4_s1_end_xfer;
    end


  //Out4_s1_waits_for_read in a cycle, which is an e_mux
  assign Out4_s1_waits_for_read = Out4_s1_in_a_read_cycle & Out4_s1_begins_xfer;

  //Out4_s1_in_a_read_cycle assignment, which is an e_assign
  assign Out4_s1_in_a_read_cycle = cpu_0_data_master_granted_Out4_s1 & cpu_0_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Out4_s1_in_a_read_cycle;

  //Out4_s1_waits_for_write in a cycle, which is an e_mux
  assign Out4_s1_waits_for_write = Out4_s1_in_a_write_cycle & 0;

  //Out4_s1_in_a_write_cycle assignment, which is an e_assign
  assign Out4_s1_in_a_write_cycle = cpu_0_data_master_granted_Out4_s1 & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Out4_s1_in_a_write_cycle;

  assign wait_for_Out4_s1_counter = 0;

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_jtag_debug_module_arbitrator (
                                            // inputs:
                                             clk,
                                             cpu_0_data_master_address_to_slave,
                                             cpu_0_data_master_byteenable,
                                             cpu_0_data_master_debugaccess,
                                             cpu_0_data_master_read,
                                             cpu_0_data_master_write,
                                             cpu_0_data_master_writedata,
                                             cpu_0_instruction_master_address_to_slave,
                                             cpu_0_instruction_master_latency_counter,
                                             cpu_0_instruction_master_read,
                                             cpu_0_jtag_debug_module_readdata,
                                             cpu_0_jtag_debug_module_resetrequest,
                                             reset_n,

                                            // outputs:
                                             cpu_0_data_master_granted_cpu_0_jtag_debug_module,
                                             cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
                                             cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
                                             cpu_0_data_master_requests_cpu_0_jtag_debug_module,
                                             cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
                                             cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
                                             cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
                                             cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
                                             cpu_0_jtag_debug_module_address,
                                             cpu_0_jtag_debug_module_begintransfer,
                                             cpu_0_jtag_debug_module_byteenable,
                                             cpu_0_jtag_debug_module_chipselect,
                                             cpu_0_jtag_debug_module_debugaccess,
                                             cpu_0_jtag_debug_module_readdata_from_sa,
                                             cpu_0_jtag_debug_module_reset,
                                             cpu_0_jtag_debug_module_reset_n,
                                             cpu_0_jtag_debug_module_resetrequest_from_sa,
                                             cpu_0_jtag_debug_module_write,
                                             cpu_0_jtag_debug_module_writedata,
                                             d1_cpu_0_jtag_debug_module_end_xfer
                                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_0_data_master_granted_cpu_0_jtag_debug_module;
  output           cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
  output           cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
  output           cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  output           cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
  output           cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
  output           cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
  output           cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
  output  [  8: 0] cpu_0_jtag_debug_module_address;
  output           cpu_0_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_0_jtag_debug_module_byteenable;
  output           cpu_0_jtag_debug_module_chipselect;
  output           cpu_0_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  output           cpu_0_jtag_debug_module_reset;
  output           cpu_0_jtag_debug_module_reset_n;
  output           cpu_0_jtag_debug_module_resetrequest_from_sa;
  output           cpu_0_jtag_debug_module_write;
  output  [ 31: 0] cpu_0_jtag_debug_module_writedata;
  output           d1_cpu_0_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input   [ 19: 0] cpu_0_instruction_master_address_to_slave;
  input            cpu_0_instruction_master_latency_counter;
  input            cpu_0_instruction_master_read;
  input   [ 31: 0] cpu_0_jtag_debug_module_readdata;
  input            cpu_0_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_arbiterlock2;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_cpu_0_jtag_debug_module;
  wire             cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
  wire             cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
  wire             cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  wire             cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module;
  wire             cpu_0_instruction_master_arbiterlock;
  wire             cpu_0_instruction_master_arbiterlock2;
  wire             cpu_0_instruction_master_continuerequest;
  wire             cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
  wire             cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
  wire             cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
  wire             cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
  wire             cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module;
  wire    [  8: 0] cpu_0_jtag_debug_module_address;
  wire             cpu_0_jtag_debug_module_allgrants;
  wire             cpu_0_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_0_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_0_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_0_jtag_debug_module_arb_addend;
  wire             cpu_0_jtag_debug_module_arb_counter_enable;
  reg     [  1: 0] cpu_0_jtag_debug_module_arb_share_counter;
  wire    [  1: 0] cpu_0_jtag_debug_module_arb_share_counter_next_value;
  wire    [  1: 0] cpu_0_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_0_jtag_debug_module_arb_winner;
  wire             cpu_0_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_0_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_0_jtag_debug_module_begins_xfer;
  wire             cpu_0_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_0_jtag_debug_module_byteenable;
  wire             cpu_0_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_0_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_0_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_0_jtag_debug_module_debugaccess;
  wire             cpu_0_jtag_debug_module_end_xfer;
  wire             cpu_0_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_0_jtag_debug_module_grant_vector;
  wire             cpu_0_jtag_debug_module_in_a_read_cycle;
  wire             cpu_0_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_0_jtag_debug_module_master_qreq_vector;
  wire             cpu_0_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  wire             cpu_0_jtag_debug_module_reset;
  wire             cpu_0_jtag_debug_module_reset_n;
  wire             cpu_0_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_0_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_0_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_0_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_0_jtag_debug_module_waits_for_read;
  wire             cpu_0_jtag_debug_module_waits_for_write;
  wire             cpu_0_jtag_debug_module_write;
  wire    [ 31: 0] cpu_0_jtag_debug_module_writedata;
  reg              d1_cpu_0_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  wire             end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
  reg              last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
  wire    [ 19: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master;
  wire    [ 19: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master;
  wire             wait_for_cpu_0_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~cpu_0_jtag_debug_module_end_xfer;
    end


  assign cpu_0_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module));
  //assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata;

  assign cpu_0_data_master_requests_cpu_0_jtag_debug_module = ({cpu_0_data_master_address_to_slave[19 : 11] , 11'b0} == 20'h0) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //cpu_0_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_0_jtag_debug_module_arb_share_set_values = 1;

  //cpu_0_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_0_jtag_debug_module_non_bursting_master_requests = cpu_0_data_master_requests_cpu_0_jtag_debug_module |
    cpu_0_instruction_master_requests_cpu_0_jtag_debug_module |
    cpu_0_data_master_requests_cpu_0_jtag_debug_module |
    cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;

  //cpu_0_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_0_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_0_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_arb_share_counter_next_value = cpu_0_jtag_debug_module_firsttransfer ? (cpu_0_jtag_debug_module_arb_share_set_values - 1) : |cpu_0_jtag_debug_module_arb_share_counter ? (cpu_0_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_0_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_0_jtag_debug_module_allgrants = |cpu_0_jtag_debug_module_grant_vector |
    |cpu_0_jtag_debug_module_grant_vector |
    |cpu_0_jtag_debug_module_grant_vector |
    |cpu_0_jtag_debug_module_grant_vector;

  //cpu_0_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_end_xfer = ~(cpu_0_jtag_debug_module_waits_for_read | cpu_0_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_end_xfer & (~cpu_0_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_0_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_0_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & cpu_0_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests);

  //cpu_0_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_0_jtag_debug_module_arb_counter_enable)
          cpu_0_jtag_debug_module_arb_share_counter <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_0_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_0_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests))
          cpu_0_jtag_debug_module_slavearbiterlockenable <= |cpu_0_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_0/data_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //cpu_0_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_0_jtag_debug_module_slavearbiterlockenable2 = |cpu_0_jtag_debug_module_arb_share_counter_next_value;

  //cpu_0/data_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_0_data_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;

  //cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;

  //cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_0_instruction_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;

  //cpu_0/instruction_master granted cpu_0/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
    end


  //cpu_0_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;

  //cpu_0_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_0_jtag_debug_module_any_continuerequest = cpu_0_instruction_master_continuerequest |
    cpu_0_data_master_continuerequest;

  assign cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_data_master_requests_cpu_0_jtag_debug_module & ~(cpu_0_instruction_master_arbiterlock);
  //cpu_0_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_0_jtag_debug_module_writedata = cpu_0_data_master_writedata;

  //mux cpu_0_jtag_debug_module_debugaccess, which is an e_mux
  assign cpu_0_jtag_debug_module_debugaccess = cpu_0_data_master_debugaccess;

  assign cpu_0_instruction_master_requests_cpu_0_jtag_debug_module = (({cpu_0_instruction_master_address_to_slave[19 : 11] , 11'b0} == 20'h0) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
  //cpu_0/data_master granted cpu_0/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
    end


  //cpu_0_data_master_continuerequest continued request, which is an e_mux
  assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_data_master_requests_cpu_0_jtag_debug_module;

  assign cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_instruction_master_requests_cpu_0_jtag_debug_module & ~((cpu_0_instruction_master_read & ((cpu_0_instruction_master_latency_counter != 0))) | cpu_0_data_master_arbiterlock);
  //local readdatavalid cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module, which is an e_mux
  assign cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module = cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read & ~cpu_0_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_jtag_debug_module_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;

  //cpu_0/instruction_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_jtag_debug_module_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;

  //cpu_0/instruction_master grant cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_instruction_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[0];

  //cpu_0/instruction_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[0] && cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;

  //cpu_0/data_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_jtag_debug_module_master_qreq_vector[1] = cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;

  //cpu_0/data_master grant cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_data_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[1];

  //cpu_0/data_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
  assign cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[1] && cpu_0_data_master_requests_cpu_0_jtag_debug_module;

  //cpu_0/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_0_jtag_debug_module_chosen_master_double_vector = {cpu_0_jtag_debug_module_master_qreq_vector, cpu_0_jtag_debug_module_master_qreq_vector} & ({~cpu_0_jtag_debug_module_master_qreq_vector, ~cpu_0_jtag_debug_module_master_qreq_vector} + cpu_0_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_0_jtag_debug_module_arb_winner = (cpu_0_jtag_debug_module_allow_new_arb_cycle & | cpu_0_jtag_debug_module_grant_vector) ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_0_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_0_jtag_debug_module_allow_new_arb_cycle)
          cpu_0_jtag_debug_module_saved_chosen_master_vector <= |cpu_0_jtag_debug_module_grant_vector ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_0_jtag_debug_module_grant_vector = {(cpu_0_jtag_debug_module_chosen_master_double_vector[1] | cpu_0_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_0_jtag_debug_module_chosen_master_double_vector[0] | cpu_0_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu_0/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_0_jtag_debug_module_chosen_master_rot_left = (cpu_0_jtag_debug_module_arb_winner << 1) ? (cpu_0_jtag_debug_module_arb_winner << 1) : 1;

  //cpu_0/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_0_jtag_debug_module_grant_vector)
          cpu_0_jtag_debug_module_arb_addend <= cpu_0_jtag_debug_module_end_xfer? cpu_0_jtag_debug_module_chosen_master_rot_left : cpu_0_jtag_debug_module_grant_vector;
    end


  assign cpu_0_jtag_debug_module_begintransfer = cpu_0_jtag_debug_module_begins_xfer;
  //assign lhs ~cpu_0_jtag_debug_module_reset of type reset_n to cpu_0_jtag_debug_module_reset_n, which is an e_assign
  assign cpu_0_jtag_debug_module_reset = ~cpu_0_jtag_debug_module_reset_n;

  //cpu_0_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_reset_n = reset_n;

  //assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest;

  assign cpu_0_jtag_debug_module_chipselect = cpu_0_data_master_granted_cpu_0_jtag_debug_module | cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
  //cpu_0_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_0_jtag_debug_module_firsttransfer = ~(cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_jtag_debug_module_any_continuerequest);

  //cpu_0_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_0_jtag_debug_module_beginbursttransfer_internal = cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_0_jtag_debug_module_arbitration_holdoff_internal = cpu_0_jtag_debug_module_begins_xfer & cpu_0_jtag_debug_module_firsttransfer;

  //cpu_0_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_0_jtag_debug_module_write = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;

  assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
  //cpu_0_jtag_debug_module_address mux, which is an e_mux
  assign cpu_0_jtag_debug_module_address = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? (shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master >> 2) :
    (shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master >> 2);

  assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
  //d1_cpu_0_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_0_jtag_debug_module_end_xfer <= 1;
      else if (1)
          d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
    end


  //cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_0_jtag_debug_module_waits_for_read = cpu_0_jtag_debug_module_in_a_read_cycle & cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_in_a_read_cycle = (cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_0_jtag_debug_module_in_a_read_cycle;

  //cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_0_jtag_debug_module_waits_for_write = cpu_0_jtag_debug_module_in_a_write_cycle & cpu_0_jtag_debug_module_begins_xfer;

  //cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_0_jtag_debug_module_in_a_write_cycle = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_0_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_0_jtag_debug_module_counter = 0;
  //cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_0_jtag_debug_module_byteenable = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_granted_cpu_0_jtag_debug_module + cpu_0_instruction_master_granted_cpu_0_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module + cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_0_data_master_arbitrator (
                                      // inputs:
                                       In0_s1_readdata_from_sa,
                                       In1_s1_readdata_from_sa,
                                       In2_s1_readdata_from_sa,
                                       clk,
                                       cpu_0_data_master_address,
                                       cpu_0_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0,
                                       cpu_0_data_master_debugaccess,
                                       cpu_0_data_master_granted_In0_s1,
                                       cpu_0_data_master_granted_In1_s1,
                                       cpu_0_data_master_granted_In2_s1,
                                       cpu_0_data_master_granted_Out0_s1,
                                       cpu_0_data_master_granted_Out1_s1,
                                       cpu_0_data_master_granted_Out2_s1,
                                       cpu_0_data_master_granted_Out3_s1,
                                       cpu_0_data_master_granted_Out4_s1,
                                       cpu_0_data_master_granted_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_granted_lcd_control_slave,
                                       cpu_0_data_master_granted_sram_16bit_512k_0_avalon_slave_0,
                                       cpu_0_data_master_granted_timer_0_s1,
                                       cpu_0_data_master_qualified_request_In0_s1,
                                       cpu_0_data_master_qualified_request_In1_s1,
                                       cpu_0_data_master_qualified_request_In2_s1,
                                       cpu_0_data_master_qualified_request_Out0_s1,
                                       cpu_0_data_master_qualified_request_Out1_s1,
                                       cpu_0_data_master_qualified_request_Out2_s1,
                                       cpu_0_data_master_qualified_request_Out3_s1,
                                       cpu_0_data_master_qualified_request_Out4_s1,
                                       cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_qualified_request_lcd_control_slave,
                                       cpu_0_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0,
                                       cpu_0_data_master_qualified_request_timer_0_s1,
                                       cpu_0_data_master_read,
                                       cpu_0_data_master_read_data_valid_In0_s1,
                                       cpu_0_data_master_read_data_valid_In1_s1,
                                       cpu_0_data_master_read_data_valid_In2_s1,
                                       cpu_0_data_master_read_data_valid_Out0_s1,
                                       cpu_0_data_master_read_data_valid_Out1_s1,
                                       cpu_0_data_master_read_data_valid_Out2_s1,
                                       cpu_0_data_master_read_data_valid_Out3_s1,
                                       cpu_0_data_master_read_data_valid_Out4_s1,
                                       cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_read_data_valid_lcd_control_slave,
                                       cpu_0_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0,
                                       cpu_0_data_master_read_data_valid_timer_0_s1,
                                       cpu_0_data_master_requests_In0_s1,
                                       cpu_0_data_master_requests_In1_s1,
                                       cpu_0_data_master_requests_In2_s1,
                                       cpu_0_data_master_requests_Out0_s1,
                                       cpu_0_data_master_requests_Out1_s1,
                                       cpu_0_data_master_requests_Out2_s1,
                                       cpu_0_data_master_requests_Out3_s1,
                                       cpu_0_data_master_requests_Out4_s1,
                                       cpu_0_data_master_requests_cpu_0_jtag_debug_module,
                                       cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave,
                                       cpu_0_data_master_requests_lcd_control_slave,
                                       cpu_0_data_master_requests_sram_16bit_512k_0_avalon_slave_0,
                                       cpu_0_data_master_requests_timer_0_s1,
                                       cpu_0_data_master_write,
                                       cpu_0_data_master_writedata,
                                       cpu_0_jtag_debug_module_readdata_from_sa,
                                       d1_In0_s1_end_xfer,
                                       d1_In1_s1_end_xfer,
                                       d1_In2_s1_end_xfer,
                                       d1_Out0_s1_end_xfer,
                                       d1_Out1_s1_end_xfer,
                                       d1_Out2_s1_end_xfer,
                                       d1_Out3_s1_end_xfer,
                                       d1_Out4_s1_end_xfer,
                                       d1_cpu_0_jtag_debug_module_end_xfer,
                                       d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                       d1_lcd_control_slave_end_xfer,
                                       d1_sram_16bit_512k_0_avalon_slave_0_end_xfer,
                                       d1_timer_0_s1_end_xfer,
                                       jtag_uart_avalon_jtag_slave_irq_from_sa,
                                       jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                       jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                       lcd_control_slave_readdata_from_sa,
                                       lcd_control_slave_wait_counter_eq_0,
                                       lcd_control_slave_wait_counter_eq_1,
                                       reset_n,
                                       sram_16bit_512k_0_avalon_slave_0_readdata_from_sa,
                                       sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0,
                                       timer_0_s1_irq_from_sa,
                                       timer_0_s1_readdata_from_sa,

                                      // outputs:
                                       cpu_0_data_master_address_to_slave,
                                       cpu_0_data_master_dbs_address,
                                       cpu_0_data_master_dbs_write_16,
                                       cpu_0_data_master_irq,
                                       cpu_0_data_master_no_byte_enables_and_last_term,
                                       cpu_0_data_master_readdata,
                                       cpu_0_data_master_waitrequest
                                    )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 19: 0] cpu_0_data_master_address_to_slave;
  output  [  1: 0] cpu_0_data_master_dbs_address;
  output  [ 15: 0] cpu_0_data_master_dbs_write_16;
  output  [ 31: 0] cpu_0_data_master_irq;
  output           cpu_0_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_0_data_master_readdata;
  output           cpu_0_data_master_waitrequest;
  input   [ 15: 0] In0_s1_readdata_from_sa;
  input   [ 15: 0] In1_s1_readdata_from_sa;
  input   [ 15: 0] In2_s1_readdata_from_sa;
  input            clk;
  input   [ 19: 0] cpu_0_data_master_address;
  input   [  1: 0] cpu_0_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0;
  input            cpu_0_data_master_debugaccess;
  input            cpu_0_data_master_granted_In0_s1;
  input            cpu_0_data_master_granted_In1_s1;
  input            cpu_0_data_master_granted_In2_s1;
  input            cpu_0_data_master_granted_Out0_s1;
  input            cpu_0_data_master_granted_Out1_s1;
  input            cpu_0_data_master_granted_Out2_s1;
  input            cpu_0_data_master_granted_Out3_s1;
  input            cpu_0_data_master_granted_Out4_s1;
  input            cpu_0_data_master_granted_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_granted_lcd_control_slave;
  input            cpu_0_data_master_granted_sram_16bit_512k_0_avalon_slave_0;
  input            cpu_0_data_master_granted_timer_0_s1;
  input            cpu_0_data_master_qualified_request_In0_s1;
  input            cpu_0_data_master_qualified_request_In1_s1;
  input            cpu_0_data_master_qualified_request_In2_s1;
  input            cpu_0_data_master_qualified_request_Out0_s1;
  input            cpu_0_data_master_qualified_request_Out1_s1;
  input            cpu_0_data_master_qualified_request_Out2_s1;
  input            cpu_0_data_master_qualified_request_Out3_s1;
  input            cpu_0_data_master_qualified_request_Out4_s1;
  input            cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_qualified_request_lcd_control_slave;
  input            cpu_0_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0;
  input            cpu_0_data_master_qualified_request_timer_0_s1;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_read_data_valid_In0_s1;
  input            cpu_0_data_master_read_data_valid_In1_s1;
  input            cpu_0_data_master_read_data_valid_In2_s1;
  input            cpu_0_data_master_read_data_valid_Out0_s1;
  input            cpu_0_data_master_read_data_valid_Out1_s1;
  input            cpu_0_data_master_read_data_valid_Out2_s1;
  input            cpu_0_data_master_read_data_valid_Out3_s1;
  input            cpu_0_data_master_read_data_valid_Out4_s1;
  input            cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_read_data_valid_lcd_control_slave;
  input            cpu_0_data_master_read_data_valid_sram_16bit_512k_0_avalon_slave_0;
  input            cpu_0_data_master_read_data_valid_timer_0_s1;
  input            cpu_0_data_master_requests_In0_s1;
  input            cpu_0_data_master_requests_In1_s1;
  input            cpu_0_data_master_requests_In2_s1;
  input            cpu_0_data_master_requests_Out0_s1;
  input            cpu_0_data_master_requests_Out1_s1;
  input            cpu_0_data_master_requests_Out2_s1;
  input            cpu_0_data_master_requests_Out3_s1;
  input            cpu_0_data_master_requests_Out4_s1;
  input            cpu_0_data_master_requests_cpu_0_jtag_debug_module;
  input            cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_0_data_master_requests_lcd_control_slave;
  input            cpu_0_data_master_requests_sram_16bit_512k_0_avalon_slave_0;
  input            cpu_0_data_master_requests_timer_0_s1;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input   [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
  input            d1_In0_s1_end_xfer;
  input            d1_In1_s1_end_xfer;
  input            d1_In2_s1_end_xfer;
  input            d1_Out0_s1_end_xfer;
  input            d1_Out1_s1_end_xfer;
  input            d1_Out2_s1_end_xfer;
  input            d1_Out3_s1_end_xfer;
  input            d1_Out4_s1_end_xfer;
  input            d1_cpu_0_jtag_debug_module_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_lcd_control_slave_end_xfer;
  input            d1_sram_16bit_512k_0_avalon_slave_0_end_xfer;
  input            d1_timer_0_s1_end_xfer;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input   [  7: 0] lcd_control_slave_readdata_from_sa;
  input            lcd_control_slave_wait_counter_eq_0;
  input            lcd_control_slave_wait_counter_eq_1;
  input            reset_n;
  input   [ 15: 0] sram_16bit_512k_0_avalon_slave_0_readdata_from_sa;
  input            sram_16bit_512k_0_avalon_slave_0_wait_counter_eq_0;
  input            timer_0_s1_irq_from_sa;
  input   [ 15: 0] timer_0_s1_readdata_from_sa;

  wire    [ 19: 0] cpu_0_data_master_address_to_slave;
  reg     [  1: 0] cpu_0_data_master_dbs_address;
  wire    [  1: 0] cpu_0_data_master_dbs_increment;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_0_data_master_irq;
  reg              cpu_0_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_run;
  reg              cpu_0_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_0_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  reg     [ 31: 0] registered_cpu_0_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~cpu_0_data_master_qualified_request_In0_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_In0_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_In1_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_In1_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_In2_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_In2_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_Out0_s1 | ~cpu_0_data_master_requests_Out0_s1) & ((~cpu_0_data_master_qualified_request_Out0_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_Out0_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_Out1_s1 | ~cpu_0_data_master_requests_Out1_s1) & ((~cpu_0_data_master_qualified_request_Out1_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_Out1_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_Out2_s1 | ~cpu_0_data_master_requests_Out2_s1) & ((~cpu_0_data_master_qualified_request_Out2_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_data_master_run = r_0 & r_1 & r_2;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = ((~cpu_0_data_master_qualified_request_Out2_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_Out3_s1 | ~cpu_0_data_master_requests_Out3_s1) & ((~cpu_0_data_master_qualified_request_Out3_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_Out3_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_Out4_s1 | ~cpu_0_data_master_requests_Out4_s1) & ((~cpu_0_data_master_qualified_request_Out4_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_Out4_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) & (cpu_0_data_master_granted_cpu_0_jtag_debug_module | ~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & 1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((~cpu_0_data_master_qualified_request_lcd_control_slave | ~cpu_0_data_master_read | (1 & lcd_control_slave_wait_counter_eq_1 & cpu_0_data_master_read)));

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = ((~cpu_0_data_master_qualified_request_lcd_control_slave | ~cpu_0_data_master_write | (1 & lcd_control_slave_wait_counter_eq_1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_sram_16bit_512k_0_avalon_slave_0) & (cpu_0_data_master_granted_sram_16bit_512k_0_avalon_slave_0 | ~cpu_0_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0) & ((~cpu_0_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | ~cpu_0_data_master_read | (1 & 1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sram_16bit_512k_0_avalon_slave_0 | ~cpu_0_data_master_write | (1 & ~d1_sram_16bit_512k_0_avalon_slave_0_end_xfer & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_timer_0_s1 | ~cpu_0_data_master_requests_timer_0_s1) & ((~cpu_0_data_master_qualified_request_timer_0_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_timer_0_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[19 : 0];

  //cpu_0/data_master readdata mux, which is an e_mux
  assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_In0_s1}} | In0_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_In1_s1}} | In1_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_In2_s1}} | In2_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
    ({32 {~cpu_0_data_master_requests_lcd_control_slave}} | lcd_control_slave_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_sram_16bit_512k_0_avalon_slave_0}} | {sram_16bit_512k_0_avalon_slave_0_readdata_from_sa[15 : 0],
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_0_data_master_requests_timer_0_s1}} | timer_0_s1_readdata_from_sa);

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_waitrequest <= ~0;
      else if (1)
          cpu_0_data_master_waitrequest <= ~((~(cpu_0_data_master_read | cpu_0_data_master_write))? 0: (cpu_0_data_master_run & cpu_0_data_master_waitrequest));
    end


  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_0_data_master_readdata <= 0;
      else if (1)
          registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_0_data_master_readdata = {32 {~cpu_0_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa;

  //irq assign, which is an e_assign
  assign cpu_0_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    timer_0_s1_irq_from_sa,
    jtag_uart_avalon_jtag_slave_irq_from_sa};

  //no_byte_enables_and_last_term, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_no_byte_enables_and_last_term <= 0;
      else if (1)
          cpu_0_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
    end


  //compute the last dbs term, which is an e_mux
  assign last_dbs_term_and_run = (cpu_0_data_master_dbs_address == 2'b10) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_sram_16bit_512k_0_avalon_slave_0;

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_