ECE 5760: Laboratory 2

Audio spectral analysis.

Introduction.

In this assignment you will implement an parallel digital audio filter bank, then use it to analyse music or your voice.

Procedures:

1. You must handle the boards only on on the ESD mat. These boards are expensive and you must be careful of them.
2. Make sure the Altera DE2 board is connected to power and to the PC as specified in the evaluation board description. Turn on the power supply with the red switch on the board. Make sure the toggle switch on the left edge of the board marked (Run/Prog) is in the Run position and leave it there at all times. The FPGA will program in the Run position. Putting the switch in the Prog position writes your design to flash memory, which you do not want to do.
3. The default top level module for the DE2 defines all of the logical i/o signals.
4. You can define the mapping from logical signal to FPGA pins (pin assignment in QuartusII) for all the pins at once by importing this file using the menu item Assignments... Import Assignments... and specifying the file name. There is no need to define pins one-by-one.
5. A hardware audio interface is shown on the DE2 page. Read ADC/DAC example 5 Verilog code.

--Using QuartusII SignalTap tool to verify your design.

Here are the steps that seem to be necssary to get SignalTap working. For more information, read the Altera tutorial on using SignalTap, an on chip logic analyzer.

1. Choose menu Tools>SignalTap
2. In the main SignalTap window, click Hardware Setup... (in the upper rigtht corner)
   and in the dialog box choose the hardware (USB-Blaster)
3. Choose menu Edit>AddNodes...
   1. Choose the appropriate Filter to simplify the list of nodes, the press List
   2. Highlight nodes and move to right-hand list using > button
   3. Click OK to get back to main SignalTap window
4. In the main SignalTap window, click the Clock ... button and choose the clock signal as in AddNodes
5. In the node panel of the main window, set up trigger conditions.
6. Compile and then load the design onto the FPGA
7. In the main SignalTap window, toggle the Data/Setup button
8. Choose menu Processing >Run Analysis

• You will design using Verilog to build the filters, video control and add the audio hardware interface. Don't use schematic entry or VHDL.
• You should implement a several hardware bandpass filters spaced linearly in log(frequency). Perhaps eight 4-pole filters/octave for a minimum frequency range of 128 Hz to 2048 Hz (4 octaves) would be about right.
• Display the smoothed output amplitude of each filter as a bar on a realtime VGA display of the spectrum. The smoothing time is long with respect to one cycle, but short compared to the dynamics of the sound source (music, speech). A switch-selectable time constant of 10 and 100 mSec should be implemented.
• Connect the audio codec input (sum left and righ channels) to the filter bank so that you can display a spectrum in realtime.
  

Be prepared to demo your design to your TA in lab.

Your written lab report should include the sections mentioned in the policy page, and :

• Filter frequencies and plots of filter response.
• A heavily commented listing of your Verilog design and GCC code.